Photo of Vijaykrishnan Narayanan

Vijaykrishnan Narayanan

Distinguished Professor

Affiliation(s):

  • School of Electrical Engineering and Computer Science
  • Computer Science and Engineering
  • Electrical Engineering

W323 Westgate Building

vxn9@psu.edu

814-863-0392

Personal or Departmental Website

Research Areas:

Interest Areas:

Energy-aware and reliable systems, soft error testing and protection, embedded Java, nano/VLSI systems, computer architecture.

 
 

 

Education

Publications

Books

  • C. Nicopoulos, N. Vijaykrishnan and C. R. Das, 2009, Network-on-Chip Architectures: A Holistic Design Exploration, Springer, pp. 175

Book, Chapters

  • X. Wu, Y. Xie and Vijaykrishnan Narayanan, 2012, Thermal-aware 3D IC Designs, Pan Stanford Publishing, Ltd., pp. 313-334
  • S. Eachempati, R. Das, Vijaykrishnan Narayanan, Y. Xie, S. Datta and C. R. Das, 2011, HeTERO: Hybrid Topology Exploration for RF Based On Chip Networks, CRC Press, pp. Ch. 6, 201-248
  • S. Eachempati, A. Gayasen, Vijaykrishnan Narayanan and M. J. Irwin, 2011, Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs, Springer, pp. 189-214
  • V. Kumar*, K. Irick*, A. Maashri* and Vijaykrishnan Narayanan, 2011, A Scalable Bandwidth-Aware Architecture for Connected Component Labeling
  • S. Eachempati, D. Park, R. Das, A. K. Mishra, N. Vijaykrishnan, Y. Xie and C. R. Das, 2010, Three-Dimensional On-Chip Interconnect Architectures, Chapman & Hall/CRC Computational Science, pp. Ch. 11, 353-382
  • A. Maashri, G. Sun, X. Dong, Y. Xie and N. Vijaykrishnan, 2010, Influence of Stacked 3D Memory/Cache Architectures on GPUs, Springer, pp. Ch. 11, 249-272
  • A. Yanamandra, S. Eachempati, N. Vijaykrishnan and M. J. Irwin, 2010, Reliability Aware Power Optimizations in DVFS-based On-Chip Networks, pp. Ch. 11, 277-292
  • V. Degalahal, R. Ramanrayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2006, Effect of Power Optimizations on Soft Error Rate
  • J. S. Hu, G. Chen, M. Kandemir and N. Vijaykrishnan, 2006, Software Power Optimisation, pp. 289-316
  • I. Kadayif, M. Kandemir, A. Choudhary, M. Karakoy, Vijaykrishnan Narayanan and M. J. Irwin, 2005, Compiler-directed Communication Energy Optimizations for Microsensor Networks, CRC Press, pp. 711-734
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, R. Brooks and M. J. Irwin, 2005, An Energy-aware Approach for Sensor Data Communication, CRC Press, pp. 697-720
  • N. Vijaykrishnan, M. J. Irwin, M. Kandemir, L. Li, G. Chen and B. Kang, 2005, Designing Energy-aware Sensor Systems, CRC Press, pp. 653-666
  • M. J. Irwin, L. Benini, N. Vijaykrishnan and M. Kandemir, 2004, Techniques for Designing Energy-aware MPSoCs, pp. Ch. 2, 21-47
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and I. Kolcu, 2004, Reducing Energy Consumption in Chip Multiprocessors using Workload Variation, pp. 123-140

Parts of Book

  • T. Theocharides, G. Link, N. Vijaykrishnan and M. J. Irwin, 2005, Networks on Chip: Interconnects for the Next Generation Systems on Chip, pp. 35-89

Journal Articles

  • Yang Xiao, Siddharth Advani, Donghwa Shin, Naehyuck Chang, John Sampson and Vijaykrishnan Narayanan, 2016, "A Saliency-Driven LCD Power Management System", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24, (8), pp. 2689–2702
  • Wei-Yu Tsai, Davis Barch, Andrew Cassidy, Mike Debole, Alexander Andreopoulos, Bryan Jackson, Myron Flickner, John Arthur, Dharmendra Modha, Jack Sampson and Vijaykrishnan Narayanan, 2016, "Always-on Speech Recognition using TrueNorth, a Reconfigurable, Neurosynaptic Processor", IEEE Transactions on Computers, (99)
  • Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta and Vijaykrishnan Narayanan, 2016, "Area-Aware Decomposition for Single-Electron Transistor Arrays", ACM Transactions on Design Automation of Electronic Systems (TODAES), 21, (4), pp. 70
  • Moon Seok Kim, William Cane-Wissing, Xueqing Li, Jack Sampson, Suman Datta, Sumeet Gupta and Vijaykrishnan Narayanan, 2016, "Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells", ACM Journal on Emerging Technologies in Computing Systems (JETC), 12, (4), pp. 38
  • Srivatsa Srinivasa, Ahmedullah Aziz, Nikhil Shukla, Xueqing Li, John Sampson, Suman Datta, Jaydeep P Kulkarni, Vijaykrishnan Narayanan and Sumeet Gupta, 2016, "Correlated Material Enhanced SRAMs With Robust Low Power Operation", IEEE Transactions on Electron Devices, 63, (12), pp. 4744–4752
  • Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta and Vijaykrishnan Narayanan, 2016, "Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24, (6), pp. 2321–2334
  • Wei-Yu Tsai, Xueqing Li, Matthew Jerry, Baihua Xie, Nikhil Shukla, Huichu Liu, Nandhini Chandramoorthy, Matthew Cotter, Arijit Raychowdhury, Donald M Chiarulli, Steven P. Levitan, Suman Datta, John Sampson, Nagarajan Ranganathan and Vijaykrishnan Narayanan, 2016, "Enabling new computation paradigms with hyperFET-an emerging device", IEEE Transactions on Multi-Scale Computing Systems, 2, (1), pp. 30–48
  • Ikenna J Okafor, Kevin M Irick and Vijaykrishnan Narayanan, 2016, "Exploration of Hardware Acceleration for a Neuromorphic Visual Classification System", The Penn State McNair Journal, pp. 77
  • Moon Seok Kim, Xueqing Li, Huichu Liu, John Sampson, Suman Datta and Vijaykrishnan Narayanan, 2016, "Exploration of low-power high-SFDR current-steering D/A converter design using steep-slope heterojunction Tunnel FETs", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24, (6), pp. 2299–2309
  • Yinan Sun, Zhe Yuan, Yongpan Liu, Xueqing Li, Yiqun Wang, Qi Wei, Yu Wang, Vijaykrishnan Narayanan and Huazhong Yang, 2016, "Maximum Energy Efficiency Tracking Circuits for Converter-less Energy Harvesting Sensor Nodes", IEEE Transactions on Circuits and Systems II: Express Briefs
  • Kaisheng Ma, Xueqing Li, Karthik Swaminathan, Yang Zheng, Shuangchen Li, Yongpan Liu, Yuan Xie, John Sampson and Vijaykrishnan Narayanan, 2016, "Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power", IEEE Micro, 36, (3), pp. 72–83
  • John Sustersic, Brad Wyble, Siddharth Advani and Vijaykrishnan Narayanan, 2016, "Towards a unified multiresolution vision model for autonomous ground robots", Robotics and Autonomous Systems, 75, pp. 221–232
  • Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta and Vijaykrishnan Narayanan, 2015, "Synthesis for Width Minimization in the Single-Electron Transistor Array", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23, (12), pp. 2862–2875
  • Dan Hammerstrom and Vijaykrishnan Narayanan, 2015, "Introduction to Special Issue on Neuromorphic Computing", Journal on Emerging Technologies in Computing Systems, 11, (4), pp. 32
  • L. Liu, X. Li, Vijaykrishnan Narayanan and Suman Datta, 2015, "A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors", IEEE Transactions on Electron Devices, 62, (3), pp. 1052-1057
  • Kaisheng Ma*, Xueqing Li, Shuangchen Li, Yongpan Liu, John Sampson, Yuan Xie and Vijaykrishnan Narayanan, 2015, "Nonvolatile Processor Architecture Exploration for Energy-HarvestingApplications", IEEE Micro, 35, (5), pp. 32–40
  • Vijaykrishnan Narayanan, Charles J. Alpert and Sara Dailey, 2015, "Editorial", IEEE Trans. on CAD of Integrated Circuits and Systems, 34, (1), pp. 1
  • Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta and Vijaykrishnan Narayanan, 2014, "Tunnel FET RF Rectifier Design for Energy Harvesting Applications", IEEE Journal on Emerg. Sel. Topics Circuits Systems, 4, (4), pp. 400–411
  • Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan and Yuan Xie, 2014, "Optimizing the NoC Slack Through Voltage and Frequency Scaling inHard Real-Time Embedded Systems", IEEE Trans. on CAD of Integrated Circuits and Systems, 33, (11), pp. 1632–1643
  • Moon Seok Kim, Huichu Liu, Xueqing Li, Suman Datta and Vijaykrishnan Narayanan, 2014, "A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter", IEEE Transactions on Electron Devices, 61, (11), pp. 3661-3667
  • Yong Cheol Peter Cho, Nandhini Chandramoorthy, Kevin M Irick and Vijaykrishnan Narayanan, 2014, "Accelerating Multiresolution Gabor Feature Extraction for Real TimeVision Applications", Signal Processing Systems, 76, (2), pp. 149–168
  • Huichu Liu, M. Cotter, Suman Datta and Vijaykrishnan Narayanan, 2014, "Soft-Error Performance Evaluation on Emerging Low Power Devices", IEEE Transactions on Device and Materials Reliability, 14, (2), pp. 732-741
  • Nikhil Shukla, Abhinav Parihar, Eugene Freeman, Hanjong Paik, Greg Stone, Vijaykrishnan Narayanan, Haidan Wen, Zhonghou Cai, Venkatraman Gopalan, Roman Engel-Herbert, Darrell G. Schlom, Arijit Raychowdhury and Suman Datta, 2014, "Synchronized charge oscillations in correlated electron systems", Scientific Reports, 4, (4964), pp. 6
  • Suman Datta, Huichu Liu and Vijaykrishnan Narayanan, 2014, "Tunnel FET technology: A reliability perspective", Microelectronics Reliability, 54, (5), pp. 861–874
  • R. Pandey, V. Saripalli, J.P. Kulkarni, Vijaykrishnan Narayanan and Suman Datta, 2014, "Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability", IEEE Electron Device Letters, 35, (3), pp. 393-395
  • R. Pandey, B. Rajamohanan, Huichu Liu, Vijaykrishnan Narayanan and Suman Datta, 2014, "Electrical Noise in Heterojunction Interband Tunnel FETs", IEEE Transactions on Electron Devices, 61, (2), pp. 552-560
  • Vijaykrishnan Narayanan, 2014, "Editorial", IEEE Trans. on CAD of Integrated Circuits and Systems, 33, (1), pp. 1
  • R. Mukundrajan, M. Cotter, V. Saripalli, M. J. Irwin, S. Datta and Vijaykrishnan Narayanan, 2013, "Design of Energy-efficient Circuits and Systems Using Tunnel Field Effect Transistors", IET Circuits, Devices & Systems (IET-CDS), Special Issue: Design Methodologies for Nanoelectronic Digital and Analogue Circuits, 7, (5), pp. 294-303
  • Y. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie and Vijaykrishnan Narayanan, 2013, "A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays", ACM Journal on Emerging Technologies in Computing Systems, 9, (1), pp. 20
  • A. Maashri, M. Cotter, N. Chandramoorthy, M. DeBole, C.-L. Yu, Vijaykrishnan Narayanan and C. Chakrabarti, 2013, "Hardware Acceleration for Neuromorphic Vision Algorithms", Signals Processing Systems, 70, (2), pp. 163-175
  • L. Liu, Vijaykrishnan Narayanan and S. Datta, 2013, "A Programmable Ferroelectric Single Electron Transisistor", Applied Physics Letters, 102, (5), pp. 4
  • K. Swaminathan, E. Kultursay, V. Saripalli, Vijaykrishnan Narayanan, M. Kandemir and S. Datta, 2013, "Steep-Slope Devices: From Dark to Dim Silicon", IEEE Micro, 33, (5), pp. 50-59
  • S. Yang, P. Gupta, M. Wolf, D. Serpanos, Y. Xie and Vijaykrishnan Narayanan, 2012, "Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling", ACM Transactions on Embedded Computing Systems (TECS), 11, (3), pp. 16
  • P. Singh, Vijaykrishnan Narayanan and D. Landis, 2012, "Targeted Random Test Generation for Power-aware Multicore Designs", ACM Transactions on Design Automation of Electronic Systems, 17, (3), pp. 25
  • C. Celik, K. Unlu, Vijaykrishnan Narayanan and M. J. Irwin, 2011, "Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC)", Nuclear Instruments and Methods in Phsyics Research A, 652, (1), pp. 370-373
  • C. Celik, K. Unlu, Vijaykrishnan Narayanan and M. J. Irwin, 2011, "Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC)", Nuclear Instruments and Methods in Phsyics Research A, 652, (1), pp. 338-341
  • V. Saripalli, G. Sun, A. Mishra, Y. Xie, S. Datta and Vijaykrishnan Narayanan, 2011, "Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors", IEEE Journal of Emerging and Selected Topics in Circuits and Systems, 1, (2), pp. 109-119
  • E. Macii, Vijaykrishnan Narayanan and K. Roy, 2011, "Advances in Design of Energy-Efficient Circuits and Systems (First Issue)", 1, (2), pp. 73-75
  • A. K. Mishra, A. Yanamandra, R. Das, S. Eachempati, R. Iyer, Vijaykrishnan Narayanan and C. R. Das, 2011, "RAFT: FPGA Architecture for 2D A Router Architecture with Frequency Tuning for On-Chip Networks", Journal of Parallel and Distributed Computing, 71, (5), pp. 625-640
  • C.-L. Yu, K. Irick, C. Chakrabarti and Vijaykrishnan Narayanan, 2011, "Multidimensional DFT IP Generator for FPGA Platforms", IEEE Transactions on Circuits and Systems 58, 1, (4), pp. 755-764
  • F. Wang, Y. Chen, X. Wu, C. Nicopoulos, Y. Xie and Vijaykrishnan Narayanan, 2011, "Variation-aware Task and Communication Mapping for MPSoC Architecture", IEEE Transactions on CAD of Integrated Circuits and Systems, 30, (2), pp. 295-307
  • D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, Vijaykrishnan Narayanan, A. Liu and S. Datta, 2011, "Experimental Staggered Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities", Applied Physics Express, 4, (2), pp. 024105-1-024105-3
  • C.-L. Yu, J. S. Kim, L. Deng, S. Kestur, Vijaykrishnan Narayanan and C. Chakrabarti, 2011, "FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data", 64, (1), pp. 109-122
  • A. K. Mishra, A. Yanamandra, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan and C. R. Das, 2010, "RAFT: A Router Architecture with Frequency Tuning for On-Chip Networks", Journal of Parallel and Distributed Computing
  • V. Saripalli, L. Liu, S. Datta and N. Vijaykrishnan, 2010, "Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits", Journal of Low Power Electronics, 6, (3), pp. 415-428
  • S. Mookerjea, D. Mohata, T. Mayer, N. Vijaykrishnan and S. Datta, 2010, "Temperature-Dependent I-V Characteristics of a Vertical In0.53Ga0.47AS Tunnel FET", IEEE Electron Device Letters, 31, (6), pp. 564-566
  • W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2010, "Total Power Optimization for Combinational Logic Using Genetic Algorithms", Journal of VLSI Signal Processing Systems, 58, (2), pp. 145-160
  • C. A. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C. R. Das and M. J. Irwin, 2010, "On the Effects of Process Variation in Network-on-Chip Architectures", IEEE Transactions on Dependable and Secure Computing (TDSC), 7, (3), pp. 240-254
  • J. S. Kim, P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun, 2009, "An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization", IEEE Transactions on Computers, 58, (12), pp. 1654-1667
  • S. Mookerjea, R. Krishnan, S. Datta and Vijaykrishnan Narayanan, 2009, "On Enhanced Miller Capacitance Effect in Inter-Band Tunnel Transistors", IEEE Electron Device Letters, 30, (10), pp. 1102-1104
  • S. Mookerjea, R. Krishnan, S. Datta and Vijaykrishnan Narayanan, 2009, "Effective Output Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation", IEEE Transactions on Electron Devices, 56, (9), pp. 2092-2098
  • M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan, 2009, "New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.", International Journal of Parallel Programming, 37, (4), pp. 417-431
  • J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2009, "Compiler-assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems", ACM Transactions on Embedded Computing Systems, 8, (4), pp. 27.1-27.29
  • M. Mutyam, F. Wang, R. Krishnan, N. Vijaykrishnan, M. Kandemir, Y. Xie and M. J. Irwin, 2009, "Process Variation Aware Adaptive Cache Architecture and Management", IEEE Transactions on Computers, 58, (7), pp. 865-877
  • S. Eachempati, N. Vijaykrishnan, A. Nieuwoudt and Y. Massoud, 2009, "Predicting the Performance and Reliability of Future Field Programmable Gate Arrays Routing Architectures with Carbon Nanotube Bundle Interconnect", IET Circuits, Devices, & Systems, 3, (2), pp. 64-75
  • T. Ragheb, A. Ricketts, M. Modal, S. Kirolos, G. Link, N. Vijaykrishnan and Y. Massoud, 2009, "Design of Thermally Robust Clock Trees using Dynamically Adaptive Clock Buffers", IEEE Transactions on Circuits and Systems (TCAS), 56, (2), pp. 374-383
  • R. Ramanaryanan, V. Degalahal, R. Krishnan, J. Kim, N. Vijaykrishnan, Y. Xie, M. Irwin and K. Unlu, 2009, "Modeling Soft Errors at Device and Logic Level for Combinational Circuits", IEEE Transactions on Dependable and Secure Computing (TDSC), 6, (3), pp. 202-216
  • S. Srinivasan, F. Angiolini, M. Ruggiero, N. Vijaykrishnan and L. Benini, 2008, "Exploring Architectural Solutions for Energy Optimizations in Bus Based SoC", IET Computers & Digital Techniques, 2, (5), pp. 347-354
  • C. Celik, K. Unlu, K. Ramakrishnan, R. Rajarman, N. Vijaykrishnan, M. J. Irwin and Y. Xie, 2008, "Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits", Journal of Radioanalytical and Nuclear Chemistry, 278, (2), pp. 509-512
  • A. Gayasen, N. Vijaykrishnan, M. Kandemir and A. Rahman, 2008, "Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues", IEEE Transactions on VLSI, 16, (7), pp. 882-893
  • S. Yang, W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan and Y. Xie, 2008, "Case Study of Reliability-Aware and Low-Power Design", IEEE Transactions on Very Large Scale Integration (VLSI), 16, (7), pp. 861-873
  • Y. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2008, "Design Space Exploration for Three-Dimensional Cache", IEEE Transactions on VLSI, 16, (4), pp. 444-455
  • S. Srinivasan, R. Krishnan, P. Mangalagiri, Y. Xie, N. Vijaykrishnan, M. J. Irwin and K. Sarpatwari, 2008, "Toward Increasing FPGA Lifetime", IEEE Transactions on Dependable and Secure Computing, 5, (2), pp. 115-127
  • R. Brooks, P. Govindaraju, M. Piretti, N. Vijaykrishnan and M. Kandemir, 2007, "On the Detection of Clones in Sensor Networks Using Random Key Predistribution", IEEE Transactions on Systems, Man, and Cybernetics, 37, (6), pp. 1246-1258
  • Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2007, "Reliability-Aware Co-synthesis for Embedded Systems", Journal of VLSI Signal Processing, 49, (1), pp. 87-99
  • F. Wang, M. Debole, X. Wu, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2007, "On-chip Bus Thermal Analysis and Optimization", IET Computer & Digital Techniques, 1, (5), pp. 590-599
  • S. Kim, N. Vijaykrishnan and M. J. Irwin, 2007, "Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set Resolution", Microprocessors and Microsystems, 31, (5), pp. 293-301
  • A. Gayasen, S. Srinivasan, N. Vijaykrishnan and M. Kandemir, 2007, "Design of Power-Aware FPGA Fabrics", International Journal of Embedded Systems, 3, (1/2), pp. 52-64
  • T. Li, J. Rubio, L. K. John, A. Sivasubramaniam and N. Vijaykrishnan, 2007, "OS-aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems", IEEE Transactions on Computers, 56, (1), pp. 2-17
  • W. Zhang, Y.-F. Tsai, D. Duarte, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2006, "Reducing Dynamic and Leakage Energy in VLIW Architectures", ACM Transactions on Embedded Computing Systems, 5, (1), pp. 1-28
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and W. Wolf, 2006, "An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain", IEEE Transactions on Circuits and Systems for Video Technology, 16, (2), pp. 191-201
  • M. Pirretti, S. Zhu, Vijaykrishnan Narayanan, P. McDaniel, M. Kandemir and R. Brooks, 2006, "The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense", International Journal of Distributed Sensor Networks, 2, (3), pp. 267-287
  • J. Lee, N. Vijaykrishnan and M. J. Irwin, 2006, "Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding", IEEE Transactions on Signal Processing, 54, (7), pp. 2559-2566
  • N. Vijaykrishnan and Y. Xie, 2006, "Reliability Concerns in Embedded System Designs", IEEE Computer Magazine, 39, (1), pp. 118-120
  • J. Lee, N. Vijaykrishnan and M. J. Irwin, 2006, "Efficient VLSI Implementation of Inverse Discrete Cosine Transform", IEEE Transactions on Circuits and Systems for Video Technology, 16, (5), pp. 655-662
  • Vijaykrishnan Narayanan and M. J. Irwin, 2005, "Editorial", Journal on Emerging Technologies in Computing Systems, 1, (1), pp. 1-6
  • V. Degalahal, L. Li, Vijaykrishnan Narayanan, M. Kandemir and M. J. Irwin, 2005, "Soft Error Issues in Low Power Caches", IEEE Transactions on VLSI, 13, (10), pp. 1157-1166
  • E.-J. Kim, G. Link, K. H. Yum, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and C. R. Das, 2005, "A Holistic Approach to Designing Energy-Efficient Cluster Interconnects", IEEE Transactions on Computers, 54, (6), pp. 660-671
  • J. S. Hu, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2005, "Analyzing Data Reuse for Cache Reconfiguration", ACM Transactions on Embedded Computer Systems (TECS), 4, (4), pp. 851-876
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2005, "Optimizing Leakage Energy Consumption in Cache Bitlines", Journal of Design Automation for Embedded Systems (DAEM), 9, (1), pp. 5-18
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2005, "An Integar Linear Programming Based Tool for Wireless Sensor Networks", Journal of Parallel and Distributed Computing (JPDC), 65, (3), pp. 247-260
  • S. Yang, W. Wolf and N. Vijaykrishnan, 2005, "Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations", IEEE Transactions on Computers, 54, (6), pp. 714-726
  • W. Zhang, Y.-F. Tsai, M. Kandemir, Vijaykrishnan Narayanan, M. J. Iriwn and V. De, 2005, "Leakage-Aware Compilation for VLIW Architectures", IEE Proceedings: Computers and Digital Techniques, 152, (2), pp. 251-260
  • I. Kadayif, M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin and A. Sivasubramaniam, 2005, "Compiler-directed High-level Energy Estimation and Optimization", ACM Transactions on Embedded Computing Systems (TECS), 4, (4), pp. 819-850
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2005, "Exploiting Temporal Loads for Low Latency and High Bandwidth Memory", IEE Proceeding: Computers and Digital Techniques, 152, (4), pp. 457-466
  • Y.-F. Tsai, D. Duarte, Vijaykrishnan Narayanan and M. J. Irwin, 2004, "Characterization and Modeling of Run-Time Techniques for Leakage Power Reduction", IEEE Transactions on Very Large Scale Integration Systems, 12, (11), pp. 1221-1233
  • G. Chen, B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli, 2004, "Studying Energy Tradeoffs in Off-loading Computation/Compilation in Java-enabled Mobile Devices", IEEE Transactions on Parallel and Distributed Systems (TPDS), 15, (9), pp. 795-809
  • A. Parikh, S. Kim, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2004, "Instruction Scheduling for Low Power", Journal of VLSI Signal Processing Systems, 37, (1), pp. 129-149
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2004, "Reducing Instruction Cache Energy Consumption Using a Compiler-based Strategy", ACM Transactions on Architecture Code Optimization (TACO), 1, (1), pp. 3-33
  • J. Juran, A. R. Hurson, N. Vijaykrishnan and S. Kim, 2004, "Data Organization and Retrieval on Parallel Air Channels", ACM/Kluwer Wireless Networks (WINET) Journal, 10, (2), pp. 183-195
  • M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif and A. Parikh, 2004, "A Compiler Based Approach for Dynamically Managing Scratch-pad Memories in Embedded Systems", IEEE Transactions on Computer Aided Design, 23, (2), pp. 243-260
  • S. Kim, S. Tomar, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Energy-Efficient Java Execution Using Local Memory and Object Co-location", IEE Proceedings: Computers and Digital Techniques, 151, (1), pp. 33-42
  • N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Kim and W. Ye, 2003, "Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework", IEEE Transactions on Computers, 52, (1), pp. 59-76
  • L. Li, I. Kadayif, Y.-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivasubramaniam, 2003, "Managing Leakage Energy in Cache Hierarchies", Journal of Instruction-level Parallelism, 5
  • S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam and M. J. Irwin, 2003, "Partitioned Instruction Cache Architecture for Energy Efficiency", ACM Transactions on Embedded Computing Systems: Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems, 2, (2), pp. 163-185
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim and W. Zhang, 2003, "Masking the Energy Behavior of Encryption Algorithms", IEE Proceedings: Computers and Digital Techniques, 150, (5), pp. 274-284
  • N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Iriwn, M. Kandemir and N. Vijaykrishnan, 2003, "Leakage Current: Moore's Law Meets Static Power", IEEE Computer, Special Issue on Power- and Temperature-Aware Computing, 36, (12), pp. 68-75
  • G. Chen, M. Kandemir, Vijaykrishnan Narayanan, N. Vijaykrishnan and M. Wolczko, 2002, "Tuning Garbage Collection for Reducing Memory System Energy in an Embedded Java Environment", ACM Transactions on Embedded Computer Systems, 1, (1), pp. 27-55
  • N. An, S. Gurumurthi, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2002, "Energy-Performance Trade-Offs for Spatial Access Methods on Memory-Resident Data", International Journal on Very Large Databases, 11, (3), pp. 179-197
  • D. E. Duarte, N. Vijaykrishnan and M. J. Irwin, 2002, "A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations", IEEE Transactions on VLSI, 10, (6), pp. 844-855
  • B. Bishop, V. Lyuboslavsky, N. Vijaykrishnan and M. J. Irwin, 2001, "Design Considerations for Databus Charge Recovery", IEEE Transactions on Very Large Scale Integration Systems, 9, (1), pp. 104-106
  • G. Esakkimuthu, H. S. Kim, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2001, "Investigating Memory System Energy Behavior Using Software and Hardware Optimizations", Special Issue in Low Power System Design of VLSI DESIGN, 12, (2), pp. 151-165
  • R. Radharkrishnan, N. Vijaykrishnan, L. K. John, A. Sivasubramaniam, J. Rubio and J. Sabarinathan, 2001, "Java runtime systems: characterization and architectural implications", IEEE Transactions on Computers, 50, (2), pp. 131-146
  • V. De La Luz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, 2001, "Hardware and Software Techniques for Controlling DRAM Power Modes", IEEE Transactions on Computers, Special Issue on Advances in High Performance Memory Systems, 50, (11), pp. 1154-1173
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Ye, 2001, "Influence of Compiler Optimizations on System Power", IEEE Transactions on VLSI Systems, 9, (6), pp. 801-804
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf, 2001, "Using Memory Compression for Energy Reduction in an Embedded Java System", Journal of Circuits, Systems and Computers, 11, (5), pp. 537-556
  • N. Vijaykrishnan and N. Ranganathan, 2000, "Supporting Object Accesses in a Java Processor", Proceedings of IEE - Computers and Digital Techniques Journal, 147, (6), pp. 435-443

Conference Proceedings

  • Sumitha George, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta, John Sampson, Sumeet Gupta and Vijaykrishnan Narayanan, 2016, "Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors", pp. 649–654
  • Xueqing Li, Kaisheng Ma, Sumitha George, John Sampson and Vijaykrishnan Narayanan, 2016, "Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures", pp. 1–6
  • Danni Wang, Sumitha George, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan and Sumeet Gupta, 2016, "Ferroelectric Transistor based Non-Volatile Flip-Flop", pp. 10–15
  • Wei-Yu Tsai, Davis R Barch, Andrew S Cassidy, Michael Vincent Debole, Alexander Andreopoulos, Bryan L Jackson, Myron D Flickner, Dharmendra S Modha, Jack Sampson and Vijaykrishnan Narayanan, 2016, "LATTE: Low-power Audio Transform with TrueNorth Ecosystem", pp. 4270–4277
  • Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Khan, Sayeef Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Gupta and others, 2016, "Nonvolatile memory design based on ferroelectric FETs", pp. 118
  • Matthew Jerry, Wei-yu Tsai, Baihua Xie, Xueqing Li, Vijaykrishnan Narayanan, Arijit Raychowdhury and Suman Datta, 2016, "Phase transition oxide neuron for spiking neural networks", pp. 1–2
  • N Shukla, W-Y Tsai, M Jerry, M Barth, Vijaykrishnan Narayanan and Suman Datta, 2016, "Ultra low power coupled oscillator arrays for computer vision applications", pp. 1–2
  • N Shukla, Suman Datta, A Parihar, Vijaykrishnan Narayanan and A Raychowdhury, 2016, "Computing with Coupled Dynamical Systems", CNNA 2016, VDE VERLAG GmbH
  • Kaisheng Ma*, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie and Vijaykrishnan Narayanan, 2015, "Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile", pp. 670–675
  • Kevin M Irick, Peter A. Zientara*, John Sampson and Vijaykrishnan Narayanan, 2015, "Cognitive cameras: Assistive vision systems", pp. 188
  • Siddharth Advani*, Brigid Smith, Yasuki Tanabe, Kevin M Irick, Matthew Cotter*, John Sampson and Vijaykrishnan Narayanan, 2015, "Visual co-occurrence network: using context for large-scale object recognition in retail", pp. 1–10
  • Siddharth Advani*, Yasuki Tanabe, Kevin M Irick, John Sampson and Vijaykrishnan Narayanan, 2015, "A scalable architecture for multi-class visual object detection", pp. 1–8
  • Moon Seok Kim, William Cane-Wissing, John Sampson, Suman Datta, Vijaykrishnan Narayanan and Sumeet Gupta, 2015, "Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMO Sand Asymmetric HTFETs", pp. 303–308
  • Ahmedullah Aziz, William Cane-Wissing, Moon Seok Kim, Suman Datta, Vijaykrishnan Narayanan and Sumeet Gupta, 2015, "Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective", pp. 333–338
  • Kaisheng Ma*, Nandhini Chandramoorthy*, Xueqing Li, Sumeet Gupta, John Sampson, Yuan Xie and Vijaykrishnan Narayanan, 2015, "Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing", pp. 339–344
  • Fen Ge, Jia Zhan, Yuan Xie and Vijaykrishnan Narayanan, 2015, "Exploring memory controller configurations for many-core systems with 3D stacked DRAMs", pp. 565–570
  • Mi Sun Park, Omesh Tickoo, Vijaykrishnan Narayanan, Mary Jane Irwin and Ravi Iyer, 2015, "Platform-aware dynamic configuration support for efficient text processing on heterogeneous system", pp. 1503–1508
  • Kaisheng Ma*, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie and Vijaykrishnan Narayanan, 2015, "Architecture exploration for ambient energy harvesting nonvolatile processors", IEEE, pp. 526–537
  • Nandhini Chandramoorthy*, Giuseppe Tagliavini, Kevin M Irick, Antonio Pullini, Siddharth Advani*, Sulaiman Al Habsi, Matthew Cotter*, John Sampson, Vijaykrishnan Narayanan and Luca Benini, 2015, "Exploring architectural heterogeneity in intelligent vision systems", IEEE, pp. 1–12
  • Karthik Swaminathan, Jagadish Kotra, Huichu Liu, John Sampson, Mahmut T Kandemir and Vijaykrishnan Narayanan, 2015, "Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures", IEEE Computer Society, pp. 221–226
  • Unsuk Heo, Xueqing Li, Huichu Liu, Sumeet Gupta, Suman Datta and Vijaykrishnan Narayanan, 2015, "A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications", pp. 304-309
  • Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta and Vijaykrishnan Narayanan, 2015, "A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays", pp. 118–123
  • N Shukla, A Parihar, M Cotter, M Barth, X Li, N Chandramoorthy, DG Schlom, Vijaykrishnan Narayanan, A Raychowdhury and Suman Datta, 2014, "Pairwise coupled hybrid vanadium dioxide-MOSFET (HVFET) oscillators for non-boolean associative computing", pp. 4
  • Matthew Cotter, Siddharth Advani, John Sampson, Kevin M Irick and Vijaykrishnan Narayanan, 2014, "A hardware accelerated multilevel visual classifier for embedded visual-assistsystems", pp. 96–100
  • Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta and Vijaykrishnan Narayanan, 2014, "Enabling Power-Efficient Designs with III-V Tunnel FETs", pp. 1–4
  • N. Chandramoorthy, K. Swaminathan, M. Cotter, Xueqing Li, Vijaykrishnan Narayanan, I. Palit, S. Hu and Kevin M Irick, 2014, "Understanding the landscape of accelerators for vision", pp. 1-6
  • Chris S. Lee, Kevin M Irick, John Sampson, Chuanjun Zhang and Vijaykrishnan Narayanan, 2014, "Exploiting natural redundancy in visual information", pp. 505–508
  • Wei-Yu Tsai, Huichu Liu, Xueqing Li and Vijaykrishnan Narayanan, 2014, "Low-power high-speed current mode logic using Tunnel-FETs", pp. 1–6
  • Siddharth Advani, Nandhini Chandramoorthy, Karthik Swaminathan, Kevin M Irick, Yong Cheol Peter Cho, John Sampson and Vijaykrishnan Narayanan, 2014, "Refresh Enabled Video Analytics (REVA): Implications on power andperformance of DRAM supported embedded visual systems", pp. 501–504
  • Huichu Liu, Mahsa Shoaran, Xueqing Li, Suman Datta, Alexandre Schmid and Vijaykrishnan Narayanan, 2014, "Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signalacquisition", pp. 57–62
  • Kaisheng Ma, Huichu Liu, Yang Xiao, Yang Zheng, Xueqing Li, Sumeet Gupta, Yuan Xie and Vijaykrishnan Narayanan, 2014, "Independently-Controlled-Gate FinFET 6T SRAM Cell Design for LeakageCurrent Reduction and Enhanced Read Access Speed", pp. 296–301
  • Xueqing Li, Wei-Yu Tsai, Huichu Liu, Suman Datta and Vijaykrishnan Narayanan, 2014, "A Low-Voltage Low-Power LC Oscillator Using the Diode-ConnectedSymFET", pp. 302–307
  • Matthew J. Cotter, Yan Fang, Steven P. Levitan, Donald M. Chiarulli and Vijaykrishnan Narayanan, 2014, "Computational Architectures Based on Coupled Oscillators", pp. 130–135
  • Karthik Swaminathan, Huichu Liu, John Sampson and Vijaykrishnan Narayanan, 2014, "An examination of the architecture and system-level tradeoffs of employingsteep slope devices in 3D CMPs", pp. 241–252
  • Karthik Swaminathan, Huichu Liu, Xueqing Li, Moon Seok Kim, John Sampson and Vijaykrishnan Narayanan, 2014, "Steep Slope Devices: Enabling New Architectural Paradigms", pp. 1–6
  • Xueqing Li, U.D. Heo, Kaisheng Ma, Vijaykrishnan Narayanan, Huichu Liu and Suman Datta, 2014, "Rf-powered systems using steep-slope devices", pp. 73-76
  • Yang Xiao, Kevin M Irick, John Sampson, Vijaykrishnan Narayanan and Chuanjun Zhang, 2014, "A task-oriented vision system", pp. 181–186
  • Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, John Sampson and Vijaykrishnan Narayanan, 2014, "Modeling steep slope devices: From circuits to architectures", pp. 1–6
  • Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Donald M. Chiarulli, Steven P. Levitan and Philip Wong, 2014, "Video analytics using beyond CMOS devices", pp. 1–5
  • Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta and Vijaykrishnan Narayanan, 2014, "Width minimization in the Single-Electron Transistor array synthesis", pp. 1–4
  • Michael Barth, Huichu L Liu, Ze Yuan, Archana Kumar, Hap Hughes, Patrick J McMarr, Jeffrey Warner, J Brad Boos, Dale McMorrow, Brian R Bennett and Vijaykrishnan Narayanan, 2014, "Total-Ionizing Dose Mechanisms in Antimony based CMOS Transistors with High-k Dielectric", pp. 4
  • R. Bijesh, H. Liu, H. Madan, W. Li, N. V. Nguyen, D. Gundlach, C. Richter, J. Maier, K. Wang, T. Clarke, M. Fastenau, D. Loubychev, W. K. Liu, Vijaykrishnan Narayanan and S. Datta, 2013, "Demonstration of In 0.9Ga0.1As/GaAs0.18Sb0.82 Near Broken-gap Tunnel FET with ION=740µA/µm,GM=700µS/µm and Gigahertz Switching Performance at VDS=0.5V", 2013 IEEE International Electron Devices Meeting (IEDM 2013), pp. 28.2.1-28.2.4
  • M. Eze, O. Ozturk and Vijaykrishnan Narayanan, 2013, "Staggered Latch Bus: A Reliable Offset Switched Architecture for Long On-chip Interconnect", Proceedings of the Twenty-First IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2013), pp. 296-301
  • Y. Xiao, C. Zhang, K. Irick and Vijaykrishnan Narayanan, 2013, "Dynamic Bandwidth Adaption Using Recognition Accuracy Prediction Through Pre-classification for Embedded Vision Systems", Proceedings of the Thirty-First IEEE International Conference on Computer Design (ICCD 2013), pp. 20-25
  • S. Datta, R. Bijesh, H. Liu, D. Mohata and Vijaykrishnan Narayanan, 2013, "Tunnel Transistors for Low Power Logic", Proceedings of the IEEE Compound Semiconductor IC Symposium (CSICS 2013), pp. 4
  • H. Liu, R. Vaddi, S. Datta and Vijaykrishnan Narayanan, 2013, "Tunnel FET-based Ultra-low Power, High-sensitivity UHF RFID Rectifier", Proceedings of the International Symposium on Low Power Electronics Design (ISLPED 2013), pp. 157-162
  • H. Liu, S. Datta and Vijaykrishnan Narayanan, 2013, "Steep Switching Tunnel FET: A Promise to Extend the Energy Efficient Roadmap for Post-CMOS Digital and Analog/RF Applications", Proceedings of the International Symposium on Low Power Electronics Design (ISLPED 2013), pp. 145-150
  • S. Park, A. Al-Maashri, Y. Xiao, K. Irick and Vijaykrishnan Narayanan, 2013, "Saliency-driven Dymnamic Configuration of HMAX for Energy-efficient Multi-object Recognition", Proceedings of the IEE Computer Society Annual Symposium on VLSI (ISVLSI 2013), pp. 139-144
  • J. Zhan, N. Stoimenov, J. Ouyang, L. Thiele, Vijaykrishnan Narayanan and Y. Xie, 2013, "Designing Energy-efficient NoC for Real-time Embedded Systems through Slack Optimization", Proceedings of the Fiftieth Design Automation Conference (DAC 2013), pp. 6
  • M. S. Park, C. Zhang, M. DeBole, S. Kestur, Vijaykrishnan Narayanan and M. J. Irwin, 2013, "Accelerators for Biologically-inspired Attention and Recognition", Proceedings of the Fiftieth Design Automation Conference (DAC 2013), pp. 6
  • S. Advani, J. Susterick, K. Irick and Vijaykrishnan Narayanan, 2013, "A Multi-Resolution Saliency Framework to Drive Foveation", pp. 2596-2600
  • C. Zhang, G. Ko, J. Choi, S.-N. Tsai, M. Kim, A. Guzmán-Rivera, R. A. Rutenbar, P. Smaragdis, M. Park, Vijaykrishnan Narayanan, H. Xin, O. Mutlu, B. Li, L. Zhao and M. Chen, 2013, "EMERALD: Characterization of Emerging Applications and Algorithms for Low-power Devices", Proceedings of the IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2013), pp. 122-123
  • N. Chandramoorthy, S. Advani, K. Irick and Vijaykrishnan Narayanan, 2013, "A Configurable Architecture for a Visual Saliency System and its Application in Retail", pp. p. 233
  • S. Datta, R. Bijesh, H. Liu, D. Mohata and Vijaykrishnan Narayanan, 2013, "Tunnel Transistors for Energy Efficient Computing", Proceedings of IEEE International Reliability Physics Symposium (IRPS 2013), pp. 6A.3.1-6A.3.7
  • Y. Xiao, K. Irick, Vijaykrishnan Narayanan, D. Shin and N. Chang, 2013, "Saliency Aware Display Power Management", Proceedings of the 2013 IEEE Design Automation and Test in Europe (DATE 2013), pp. 1203-1208
  • M. Cotter, H. Liu, S. Datta and Vijaykrishnan Narayanan, 2013, "Evaluation of Tunnel FET-based Flip-flop Designs for Low Power, High Performance Applications", Proceedings of the International Symposium on Quality Electronic Design (ISQED 2013), pp. 430-437
  • H. Liu, M. Cotter, Vijaykrishnan Narayanan and S. Datta, 2013, "Evaluation Soft Error Rate Immunity in Emerging Devices", Proceedings of the Thirty-Eighth Annual Government Microcircuit Applications & Critical Technology Conference (GOMACTech 2013)
  • Y.-Y. Chang, C.-Y. Huang, M. Poremba, Vijaykrishnan Narayanan, Y. Xie and C.-T. King, 2013, "TS-Router: On Maximizing the Quality-of-Allocation in the On-Chip Network", Proceedings of the Nineteenth IEEE International Symposium on High Performance Computer Architecture (HPCA 2013), pp. 390-399
  • C.-E. Chiang, L.-F. Tang, C.-Y. Wang, C.-Y. Huang, Y.-C. Chen, S. Datta and Vijaykrishnan Narayanan, 2013, "On Reconfigurable Single-Electron Transistor Arrays Synthesis Using Reordering Techniques", Proceedings of the 2013 IEEE Design Automation and Test in Europe (DATE 2013), pp. 1807-1812
  • J. Henkel, Vijaykrishnan Narayanan, S. Parameswaran and J. Teich, 2013, "Run-time Adaption for Highly-complex Multi-core Systems", Proceedings of the Eleventh International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2013), pp. 8
  • Y.-Y. Chang, C.-Y. Huang, Vijaykrishnan Narayanan and C.-T. King, 2013, "ShieldUS: A Novel Design of Dynamic Shielding for Eliminating 3D TSV Crosstalk Coupling Noise", Proceedings of the Eighteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2013), pp. 675-680
  • H. Liu*, M. Cotter*, S. Datta and Vijaykrishnan Narayanan, 2012, "Technology Assessment of Si and III-V FinFETs and III-V Tunnel FETs From Soft Error Rate Perspective", Proceedings of the IEEE International Electron Devices Meeting (IEDM 2012), pp. 577-580
  • Y. Cho*, N. Chandramoorthy*, K. Irick and Vijaykrishnan Narayanan, 2012, "Multiresolution Gabor Feature Extraction for Real Time Applications", Proceedings of the 2012 IEEE Workshop on Signal Process Systems (SIPS 2012), pp. 55-60
  • E. Kultursay, K. Swaminathan*, V. Saripalli*, Vijaykrishnan Narayanan, M. Kandemir and S. Datta, 2012, "Performance Enhancement Under Power Constraints Using Heterogeneous CMOS-TFET Multicores", Proceedings of the Tenth International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2012), pp. 245-254
  • R. Munkundrajan*, M. Cotter*, V. Saripalli*, M. J. Irwin, S. Datta and Vijaykrishnan Narayanan, 2012, "Ultra Low Power Circuit Design Using Tunnel FETs", Proceedings of the IEE Computer Society Annual Symposium on VLSI (ISVLSI 2012), pp. 153-158
  • A. Al-Maashri*, M. DeBole, M. Cotter*, N. Chandramoorthy*, Y. Xiao, Vijaykrishnan Narayanan and C. Chakrabarti, 2012, "Accelerating Neuromorphic Vision Algorithms for Recognition", Proceedings of the Forty-Ninth Annual Design Automation Conference (DAC 2012), pp. 579-584
  • A. Jog, A. Mishra, C. Xu, Vijaykrishnan Narayanan, Y. Xie, R. Iyer and C. R. Das, 2012, "Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs", Proceedings of the Forty-Ninth Annual Design Automation Conference (DAC 2012), pp. 243-252
  • H. Liu*, D. Mohata, A. Nidhi, V. Saripalli*, Vijaykrishnan Narayanan and S. Datta, 2012, "Exploration of Vertical MOSFET and Tunnel FET Device Architecture for Sub 10nm Node Applications", Proceedings of the Seventieth Annual Device Research Conference (DRC 2012), pp. 233-234
  • N. Agrawal, V. Saripalli*, Vijaykrishnan Narayanan, Y. Kumura, R. Arghavani and S. Datta, 2012, "Will Strong Quantum Confinement Effect Limit Low VCC Logic Application of III-V FinFETs", Proceedings of the Seventieth Annual Device Research Conference (DRC 2012), pp. 231-232
  • D. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastneau, D. Loubychev, A. K. Liu, T. S. Mayer, Vijaykrishnan Narayanan and S. Datta, 2012, "Demonstration of Improved Heteroepitaxy, Scaled Gate Stack and Reduced Interface States Enabling Heterojunction Tunnel FETs with Hihg Drive Current and High On-Off Ratio", Proceedings of the IEEE Symposia on VLSI Technology and Circuits, pp. 53-54
  • J. Xie*, Vijaykrishnan Narayanan and Y. Xie, 2012, "Mitigating Electromigration of Power Supply Networks using Bidirectional Current Stress", Proceedings of the Great Lakes Symposium on VLSI (VLSI 2012), pp. 299-32
  • S.-M. Park*, S. Kestur*, J. Sabarad*, Vijaykrishnan Narayanan and M. J. Irwin, 2012, "An FPGA-based Accelerator for Cortical Object Classification", Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), pp. 691-696
  • P. Singh, Vijaykrishnan Narayanan and D. Landis, 2012, "Hazard Driven Test Generation for SMT Processors", Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), pp. 256-259
  • J. Sabarad*, S. Kestur*, S.-M. Park*, D. Dantara*, Vijaykrishnan Narayanan, Y. Chen and D. Khosla, 2012, "A Reconfigurable Accelerator for Neuromorphic Object Recognition", Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012), pp. 813-818
  • K. Swaminathan*, R. Pisolkar, C. Xu and Vijaykrishnan Narayanan, 2012, "When to Forget: A System-level Perspective on STT-RAMs", Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012), pp. 311-316
  • S. Park*, Y. Cho*, K. Irick and Vijaykrishnan Narayanan, 2012, "A Reconfigurable Platform for the Design and Verification of Domain-specific Accelerators", Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012), pp. 108-113
  • S. Kestur*, S.-M. Park*, J. Sabarad*, D. Dantara*, Vijaykrishnan Narayanan, Y. Chen and D. Khosla, 2012, "Emulating Mammalian Vision on Reconfigurable Hardware", Proceedings of the IEEE Twentieth Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012), pp. 141-148
  • K. Swaminathan*, E. Kultursay, V. Saripalli*, Vijaykrishnan Narayanan and M. Kandemir, 2012, "Design Space Evaluation of Workload-specified Last Level Caches", Proceedings of the International Symposium on Low Power Electronics Design (ISLPED 2012), pp. 243-248
  • L. Liu, V. Saripalli, Vijaykrishnan Narayanan and S. Datta, 2011, "Device Circuit Co-Design Using Classical and Non-Classical III-V Multi-Gate Quantum-Well FETs (MuQFETs)", Proceedings of the 2011 IEEE International Electron Devices Meeting (IEDM)
  • D. K. Mohata, R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, Vijaykrishnan Narayanan, J. Fastenau, D. Loubychev, A. Liu and S. Datta, 2011, "Demonstration of MOSFET-Like On-Current Performance in Arsenide/ Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications", Proceedings of the 2011 IEEE International Electron Devices Meeting (IEDM), pp. 4
  • M. DeBole, A. Al Maashri, M. Cotter, C.-L. Yu, C. Chakrabarti and Vijaykrishnan Narayanan, 2011, "A Framework for Accelerating Neuromorphic-Vision Algorithms on FPGAs", Proceedings of the International Conference on Computer-Aided Design (ICCAD 2011), pp. 810-813
  • M. DeBole, C.-L. Yu, A. Al Maashri, M. Cotter, C. Chakrabarti and Vijaykrishnan Narayanan, 2011, "FPGA-Accelerator System for Computing Biologically-Inspired Feature Extraction Models", Proceedings of the Asilomar Conference on Signals, Systems, and Computers, pp. 751-755
  • A. Al Maashri, M. DeBole, C.-L. Yu, Vijaykrishnan Narayanan and C. Chakrabarti, 2011, "A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms", Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2011), pp. 355-360
  • Y. Cho, S. Bae, Y. Jin, K. Irick and Vijaykrishnan Narayanan, 2011, "Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA", Proceedings of the Twenty-First International Conference on Field Programmable Logic and Applications (FPL 2011), pp. 311-316
  • K. Swaminathan, E. Kultursay, V. Saripalli, Vijaykrishnan Narayanan, M. Kandemir and S. Datta, 2011, "Improving Energy Efficiency of Multi-Threaded Applications using Heterogeneous CMOS-TFET Mutlicores", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2011), pp. 247-252
  • K. Swaminathan, R. Mukundrajan, N. Soundararajan and Vijaykrishnan Narayanan, 2011, "Towards Resilient Micro-architectures: Datapath Reliability Enhancement using STT-MRAM", Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2011 (ISVLSI 2011), pp. 236-241
  • H.-W. Chen, S. Srinivasan, Y. Xie and Vijaykrishnan Narayanan, 2011, "Impact of Circuit Degradation on FPGA Design Security", Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2011 (ISVLSI 2011), pp. 230-235
  • Vijaykrishnan Narayanan, S. Park, S. Kestur and K. Irick, 2011, "Accelerating Neuromorphic Vision on FPGAs", Proceedings of the Embedded Computer Vision Workshop, in conjunction with CVPR 2011, pp. 103-108
  • V. Saripalli, J. Kulkarni, S. Datta and Vijaykrishnan Narayanan, 2011, "Variation-Tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), pp. 45-52
  • Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie and Vijaykrishnan Narayanan, 2011, "Automated Mapping for Reconfigurable Single Electron Transistor Arrays", Proceedings of the Forty-Eighth Design Automation Conference (DAC 2011), pp. 878-883
  • V. Saripalli, A. Mishra, S. Datta and Vijaykrishnan Narayanan, 2011, "An Energy-Efficient Heterogeneous CMP Based on Hybrid TFET-CMOS Cores", Proceedings of the Forty-Eighth Design Automation Conference (DAC 2011), pp. 729-734
  • S. Kestur, K. Irick, S. Park, A. Al-Maashri, Vijaykrishnan Narayanan and C. Chakrabarti, 2011, "An Algorithm-architecture Co-design Framework for Gridding Reconstruction Using FPGAs", Proceedings of the Forty-Eighth Design Automation Conference (DAC 2011), pp. 585-590
  • A. Mishra, Vijaykrishnan Narayanan and C. R. Das, 2011, "A Case for Heterogeneous On-Chip Interconnects for CMPs", Proceedings of the Thirty-Eighth International Symposium on Computer Architecture (ISCA 2011), pp. 389-400
  • A. Mishra, X. Dong, G. Sun, Y. Xie, Vijaykrishnan Narayanan and C. R. Das, 2011, "Architecting On-chip Interconnects for Stacked 3D STT-RAM Caches in CMPs", Proceedings of the Thirty-Eighth International Symposium on Computer Architecture (ISCA 2011), pp. 69-80
  • L. Liu, V. Saripalli, Vijaykrishnan Narayanan and S. Datta, 2011, "Experimental Investigation of Scalability and Transport in In0:7Ga0:3As Multi-Gate Quantum Well FET (MuQFET)", Proceedings of the Sixty-Ninth Annual Device Research Conference (DRC 2011), pp. 17-18
  • S. Bae, Y. Cho, S. Park, K. Irick, Y. Jin and Vijaykrishnan Narayanan, 2011, "An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization", Proceedings of the Nineteenth Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), pp. 41-48
  • Vijaykrishnan Narayanan, V. Saripalli, R. Mukundrajan, G. Sun, K. Swaminathan, Y. Xie and S. Datta, 2011, "Enabling Architectural Innovations using Non-Volatile Memory", Proceedings of the Twenty-First ACM Great Lakes Symposium on VLSI (GLSVLSI 2011), pp. 439-444
  • S. Kestur, D. Dantara and Vijaykrishnan Narayanan, 2011, "SHARC: A Streaming Model for FPGA Accelerators and its Application to Saliency", Proceedings of the Design, Automation & Test in Europe (DATE 2011), pp. 1237-1242
  • S. Kestur, D. Dantara and Vijaykrishnan Narayanan, 2011, "A Streaming FPGA Implementation of a Steerable Filter for Real-time Applications", Proceedings of the Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2011), pp. p. 281
  • S. M. Bae and N. Vijaykrishnan, 2010, "Thermal Gradient Aware Clock Skew Scheduling for FPGAs", Proceedings of the Twentieth International Conference on Field Programmable Logic and Applications (FPL 2010), pp. 101-106
  • V. Sampath Kumar, K. Irick, A. Al Maashri and N. Vijaykrishnan, 2010, "A Scalable Bandwidth Aware Architecture for Connected Component Labeling", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), pp. 116-121
  • N. Vijaykrishnan, A. Al Mashri, K. Irick, M. DeBole and S. Park, 2010, "AutoFLEX: A Framework for Image Processing Applications on Multi-FPGA Systems", Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2010), pp. 59-66
  • N. Soundararajan, A. Sivasubramaniam and N. Vijaykrishnan, 2010, "Characterizing Soft-error Vulnerability of Mulicores Running Multi-threaded Applications", Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2010), pp. 379-380
  • V. Saripalli, D. K. Mohata, S. Mookerjea, S. Datta and N. Vijaykrishnan, 2010, "Low Power Loadless 4T SRAM Cell Based on Degenerately Doped Source (DDS) In_0.53 GA_0.47 as Tunnel FETs", Proceedings of the IEEE Device Research Conference (DRS 2010), pp. 101-102
  • S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer and N. Vijaykrishnan, 2010, "Non-silicon Logic Elements on Silicon for Extreme Voltage Scaling", Proceedings of the Silicon Nanoelectronics Workshop (SNW), pp. 15-16
  • S. Kestur, S. Park, K. Irick and N. Vijaykrishnan, 2010, "Accelerating the Nonuniform Fast Fourier Transform Using FPGAs", Proceedings of the Eighteenth IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), pp. 19-26
  • A. Ricketts, N. Vijaykrishnan, J. Singh and D. Pradhan, 2010, "Investigating the Impact of NBTI on Different Power Saving Cache Strategies", Proceedings of the Design, Automation & Test in Europe (DATE 2010), pp. 592-597
  • A. Rathi, M. DeBole, W. Ge, R. Collins and Vijaykrishnan Narayanan, 2010, "A GPU Based Implementation of Center-Surround Distribution Distance for Feature Extraction and Matching", Proceedings of the Design, Automation & Test in Europe (DATE 2010), pp. 172-177
  • C.-L. Yu, C. Chakrabarti, S. Park and N. Vijaykrishnan, 2010, "Bandwidth-intensive FPGA Architecture for Multi-dimensional DFT", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2010), pp. 1486-1489
  • V. Saripalli, N. Vijaykrishnan and S. Datta, 2010, "Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors", Proceedings of the Twenty-Third International Conference on VLSI Design (VLSI Design 2010), pp. 399-404
  • A. Yanamandra, S. Eachempati, N. Soundararajan, N. Vijaykrishnan, M. J. Irwin and R. Krishnan, 2010, "Optimizing Power and Performance for Reliable On-Chip Networks", Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp. 431-436
  • J. Singh, R. Krishnan, S. Mookerjea, S. Datta and N. Vijaykrishnan, 2010, "A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications", Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp. 181-186
  • S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, N. Vijaykrishnan, D. Schlom, A. Liu and S. Datta, 2009, "Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications", Proceedings of the IEEE International Electron Devices Meeting (IEDM 2009)
  • A. Mishra, R. Das, S. Eachempati, N. Vijaykrishnan and C. R. Das, 2009, "A Case for Dynamic Frequency Tuning in On-Chip Networks", Proceedings of the Forty-Second International Symposium on Microarchitecture (MICRO-42), pp. 292-303
  • V. Saripalli, N. Vijaykrishnan and S. Datta, 2009, "Ultra Low Energy Binary Decision Diagram Circuits using Few Electron Transistors", Proceedings of the Workshop on Nano-Bio Sensing Paradigms and Applications, in conjunction with Nano-Net 2009, pp. 200-209
  • A. Al'Maashri, G. Sun, X. Dong, N. Vijaykrishnan and Y. Xie, 2009, "3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis", Proceedings of the International Conference on Computer Design (ICCD 2009), pp. 254-259
  • J. S. Kim, C.-L. Yu, L. Deng, S. Kestur, Vijaykrishnan Narayanan and C. Chakrabarti, 2009, "FPGA Architecture for 2D Fast Fourier Transform Based on 2D Decomposition for Large-Sized Data", Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2009), pp. 121-126
  • K. Irick, M. DeBole, S. Park and N. Vijaykrishnan, 2009, "A Scalable Multi-FPGA Framework for Real-time Digital Signal Processing", Proceedings of SPIE Optics+Photonics Conference, pp. 6
  • S. Datta and N. Vijaykrishnan, 2009, "Green Transistors to Green Architectures", Proceedings of the 2009 International Symposium on Low Power Electronics and Design (ISLPED 2009), pp. 429-430
  • Y. Xie, S. Eachempati, A. Yanamandra, N. Vijaykrishnan and M. J. Irwin, 2009, "Power and Area Reduction using Carbon Nanotube Bundle Interconnect in Global Clock Tree Distribution Network", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009), pp. 51-56
  • S. Bae, R. Krishnan and N. Vijaykrishnan, 2009, "A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009), pp. 193-198
  • P. Mangalagiri and N. Vijaykrishnan, 2009, "Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009), pp. 61-66
  • S. Bae, P. Mangalagiri and N. Vijaykrishnan, 2009, "Exploiting Clock Skew Scheduling for FPGA", Proceedings of the Design Automation & Test in Europe (DATE 2009), pp. 1524-1529
  • R. Das, S. Eachempati, A. K. Mishra, N. Vijaykrishnan and C. R. Das, 2009, "Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs", Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture (HPCA-15), pp. 175-186
  • A. Yanamandra, M. J. Irwin, N. Vijaykrishnan, M. Kandemir and S. H. K. Narayanan, 2009, "In-Network Caching for Chip Multiprocessors", Springer-Verlag LNCS, 5409, pp. 373-388
  • S. Sridharan, M. DeBole, G. Sun, Y. Xie and N. Vijaykrishnan, 2009, "A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner", Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp. 763-768
  • M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, L. Hong, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan, 2009, "A Framework for Estimating NBTI Degradation of Microarchitectural Components", Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp. 455-460
  • J. Henkel, N. Vijaykrishnan, S. Parameswaran and R. Ragel, 2009, "Security and Dependability of Embedded Systems: A Computer Architects' Perspective", Proceedings of the Twenty-Second International Conference on VLSI Design (VLSI Design 2009), pp. 30-32
  • P. Mangalagiri, S. Bae, R. Krishnan, N. Vijaykrishnan, Y. Xie and T. Tuan, 2008, "Thermal-Aware Reliability Analysis for Platform FPGAs", Proceedings of the International Conference on Computer Aided Design (ICCAD 2008), pp. 722-727
  • K. Ramakrishnan, N. Vijaykrishnan and Y. Xie, 2008, "Comparative Analysis of NBTI Effects on Low Power and High Performance Flip-Flops", Proceedings of the XXVI International Conference on Computer Design (ICCD 2008), pp. 200-205
  • L. Deng, C.-L. Yu, C. Chakrabarti, J. Kim and N. Vijaykrishnan, 2008, "Efficient Image Reconstruction Using Partial 2D Fourier Transform", Proceedings of the 2008 IEEE Workshop on Signal Processing Systems (SIPS 2008), pp. 49-54
  • N. Soundararajan, N. Vijaykrishnan and A. Sivasubramaniam, 2008, "Impact of DVFS on the Architectural Vulnerability of GALS Architctures", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2008), pp. 351-356
  • N. Soundararajan, A. Yanamandra, C. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, 2008, "Analysis and Solutions to Issue Queue Process Variation", Proceedings of the Thirty-Eighth Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2008), pp. 11-21
  • D. Park, S. Eachempati, R. Das, A. K. Mishra, N. Vijaykrishnan, Y. Xie and C. R. Das, 2008, "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture", Proceedings of the International Symposium on Computer Architecture (ISCA 2008), pp. 251-261
  • S. Eachempati, V. Saripalli, N. Vijaykrishnan and S. Datta, 2008, "Reconfigurable BDD Based Quantum Circuits", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch 2008), pp. 61-67
  • P. Mangalagiri, K. Sarpatwari, A. Yanamandra, N. Vijaykrishnan, Y. Xie, M. J. Irwin and O. A. Karim, 2008, "A low-power Phase Change Memory Based Hybrid Cache Architecture", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2008), pp. 395-398
  • K. Irick, N. Vijaykrishnan, M. DeBole and A. Gayasen, 2008, "A Hardware Efficient Support Vector Machine Architecture for FPGA", Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), pp. 304-305
  • R. Krishnan, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin and K. Unlu, 2008, "Hierarchical Soft Error Estimation Tool (HSEET)", Proceedings of the Ninth International Symposium on Quality Electronic Design (ISQED 2008), pp. 680-683
  • R. Das, A. K. Mishra, C. Nicopoulos, D. Park, N. Vijaykrishnan, R. Iyer and C. R. Das, 2008, "Performance and Power Optimization through Data Compression in Network-on-Chip Architectures", Proceedings of the Fourteenth International Symposium on High Performance Computer Architecture (HPCA 2008), pp. 215-225
  • D. Atienza, G. De Micheli, L. Benini, J. L. Ayala, P. G. Del Valle, M. DeBole and N. Vijaykrishnan, 2008, "Reliability-Aware Design for Nanometer-Scale Devices", Proceedings of the Thirteenth IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2008), pp. 549-554
  • J. Kim, P. Mangalagiri, K. Irick, N. Vijaykrishnan, M. Kandemir, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis and X. Sun, 2007, "TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform", Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007), pp. 6
  • K. Irick, M. DeBole, N. Vijaykrishnan, R. Sharma, H. Moon and S. Mummareddy, 2007, "Unified Streaming Architecture for Real Time Face Detection and Gender Classification", Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007)
  • D. Park, R. Das, C. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer and C. R. Das, 2007, "Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects", Proceedings of the Fifteenth Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), pp. 15-20
  • J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan and C. R. Das, 2007, "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures", Proceedings of the Thirty-Fourth Annual International Symposium on Computer Architecture (ISCA 2007), pp. 138-149
  • M. Mutyam and N. Vijaykrishnan, 2007, "Working with Process Variation Aware Caches", Proceedings of the Design, Automation and Test in Europe (DATE'07), pp. 1152-1157
  • M. Mondal, A. Ricketts, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan and Y. Massoud, 2007, "Thermally Robust Clocking Schemes for 3D Integrated Circuits", Proceedings of the Design, Automation and Test in Europe (DATE'07), pp. 1206-1211
  • S. Eachempati, A. Nieuwoudt, A. Gayasen, Y. Massoud and N. Vijaykrishnan, 2007, "Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures", Proceedings of the Design, Automation and Test in Europe (DATE'07), pp. 307-312
  • R. Krishnan, R. Ramanarayanan, S. Srinivasan, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2007, "Variation Impact on SER of Combinational Circuits", Proceedings of the International Society for Quality Electronic Design (ISQED 2007), pp. 911-916
  • A. Mupid, M. Mutyam, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2007, "Variation Analysis of CAM Cells", Proceedings of the Eighth International Symposium on Quality Electronic Design (ISQED 2007), pp. 333-338
  • M. Mondal, A. Ricketts, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan and Y. Massoud, 2007, "Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers", Proceedings of the International Society for Quality Electronic Design (ISQED 2007), pp. 67-72
  • B. Vaidyanathan, W. Hung, F. Wang, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2007, "Architecting Microprocessor Components in 3D Design Space", Proceedings of the Twentieth International Conference on VLSI Design, pp. 103-108
  • K. Ramakrishnan, R. S. Srinivasan, N. Vijaykrishnan and Y. Xie, 2007, "Impact of NBTI on FPGAs", Proceedings of the International Conference on VLSI Design, pp. 717-722
  • G. Chen, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2006, "Object Duplication for Improving Reliability", Proceedings of the Eleventh Asia and South Pacific Design Automation Conference (ASP-DAC 2006), pp. 140-145
  • T. Richardson, C. Nicopoulos, N. Vijaykrishnan, D. Park, Y. Xie and C. R. Das, 2006, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks", Proceedings of IEEE International Conference on VLSI Design, pp. 657-664
  • R. Ramanarayanan, J. S. Kim, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2006, "SEAT-LA: A Soft Error Analysis tool for Combinational Logic", Proceedings of Nineteenth International Conference on VLSI Design, pp. 499-502
  • I. Lin, S. Srinivasan, Vijaykrishnan Narayanan and N. Dhanwada, 2006, "Transaction Level Error Susceptibility Model for SoC Bus Based SoC Architectures", Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006), pp. 775-780
  • G. Link and N. Vijaykrishnan, 2006, "Thermal Trends in Emerging Technologies", Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006), pp. 625-632
  • F. Wang, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2006, "On-chip Bus Thermal Analysis and Optimization", Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006), pp. 850-855
  • A. J. Ricketts, K. Irick, N. Vijaykrishnan and M. J. Irwin, 2006, "Priority Scheduling in Digital Microfluidics-Based Biochips", Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006), pp. 329-334
  • T. Theocharides, Vijaykrishnan Narayanan and M. J. Irwin, 2006, "A Parallel Architecture for Hardware Face Detection", Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006), pp. 452-454
  • M. Mutyam, M. Eze, N. Vijaykrishnan and Y. Xie, 2006, "Delay and Energy Efficient Data Transmission for On-Chip Buses", Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006), pp. 355-360
  • S. Srinivasan and N. Vijaykrishnan, 2006, "Variation Aware Placement Scheme for FPGAs", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), pp. 422-424
  • J. Kim, C. A. Nicopoulos, D. Park, N. Vijaykrishnan and C. R. Das, 2006, "Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures", Special Workshop on Future Interconnects and Networks on Chip, in conjunction with the Design, Automation and Test in Europe (DATE 06)
  • J. Kim, C. A. Nicopoulos, D. Park, N. Vijaykrishnan and C. R. Das, 2006, "A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks", Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006), pp. 4-15
  • D. Park, C. A. Nicopoulos, J. Kim, N. Vijaykrishnan and C. R. Das, 2006, "Exploring Fault-Tolerant Network-on-Chip Architectures", Proceedings of the International Conference on Dependable Systems and Networks (DSN-2006), pp. 93-102
  • R. Ramanarayanan, K. Krishnan, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2006, "Temperature and Voltage Scaling Effects on Electrical Masking", Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006), pp. 4
  • A. Gayasen, Vijaykrishnan Narayanan, M. Kandemir and A. Rahman, 2006, "Switch Box Architectures for Three-Dimensional FPGAs", Proceedinsg of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 2
  • C. A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan and C. R. Das, 2006, "ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers", Proceedings of the International Symposium on Microarchitecture (MICRO 06), pp. 333-346
  • B. Vaidyanathan, Y. Xie, N. Vijaykrishnan and R. Luo, 2006, "Leakage Optimized DECAP Design for FPGAs", Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), pp. 5
  • P. Sundararajan, A. Gayasen, Vijaykrishnan Narayanan and T. Tuan, 2006, "Thermal Characterization and Optimization in Platform FPGAs", Proceedings International Conference on Computer Aided Design (ICCAD-2006), pp. 443-447
  • P. Sundararajan, S. Krishnamurthy, N. Vijaykrishnan, K. Chaudhary and R. Jayaraman, 2006, "Performance Improvements Through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs", Proceedings of the IEEE International System on Chip Conference (SOCC 2006), pp. 105-106
  • G. Chen, L. Xue, J. Kim, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir and N. Vijaykrishnan, 2006, "Using Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations", Proceedings of the IEEE International System on Chip Conference (SOCC 2006), pp. 113-114
  • S. Srinivasan, R. Ramadoss and Vijaykrishnan Narayanan, 2006, "Process Variation Aware Parallelization Strategies for MPSoCs", Proceedings of the IEEE International System on Chip Conference (SOCC 2006), pp. 179-184
  • D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan and C. R. Das, 2006, "A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects", Proceedings of the First International Conference on Nano-Networks (Nano-Net 2006), pp. 6
  • S. Srinivasan, M. Prasanth, S. Karhink, Y. Xie and Vijaykrishnan Narayanan, 2006, "FLAW: FPGA Lifetime Awareness", Proceedings of the Forty-Third Design Automation Conference (DAC 2006), pp. 630-635
  • F. Li, C. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan and M. Kandemir, 2006, "Design and Management of 3D Chip Multiprocessors using Network-in-memory", Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006), pp. 130-141
  • M. Mutyam, F. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2006, "Compiler Directed Thermal Management for VLIW Functional Units", Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006), pp. 163-172
  • B. Vaidyanathan, Y. Xie, Vijaykrishnan Narayanan and H. Zheng, 2006, "Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits", Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006), pp. 4
  • W.-L. Hung, G. Link, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2006, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors", Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006), pp. 98-104
  • S. Yang, W. Wolf, N. Vijaykrishnan and Y. Xie, 2006, "Reliability-aware SOC Voltage Islands Partition and Floorplan", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), pp. 341-347
  • K. Veezhinathan, Sk. Noor Mahammad, V. Muralidaran and N. Vijaykrishnan, 2005, "Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGA", Proceedings of the Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD '05)
  • S. Srinivasan, F. Angiolini, M. Ruggiero, N. Vijaykrishnan and L. Benini, 2005, "Simultaneous Memory and Bus Partitioning for SoC Architectures", Proceedings of the IEEE International SoC Conference (SOCC 2005), pp. 125-128
  • J. Kim, D. Park, C. Nicopoulos, N. Vijaykrishnan and C. R. Das, 2005, "Design and Analysis of an NoC Architecture from Performance, Reliability and Energy Perspective", Proceedings of the First Symposium on Architectures for Networking and Communication Systems (ANCS 2005), pp. 173-182
  • M. Pirretti, N. Vijaykrishnan, M. Kandemir and R. Brooks, 2005, "Realistic Models for Sensor Networks Using Key Predistribution Schemes", Proceedings of the Innovations and Commercial Applications of Distributed Sensor Networks Symposium (ICA DSN)
  • M. Pirretti, S. Zhu, N. Vijaykrishnan, P. McDaniel, M. Kandemir and R. Brooks, 2005, "The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense", Proceedings of the Innovations and Commercial Applications of Distributed Sensor Networks Symposium (ICA DSN)
  • W. Hung, G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada and J. Conner, 2005, "Temperature-Aware Voltage Islands Architecting in System-on-Chip Design", Proceedings of the IEEE International Conference on Computer Design (ICCD 2005), pp. 689-696
  • Y. Tsai, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2005, "Three-dimensional cache design using 3DCacti", Proceedings of the IEEE International Conference on Computer Design (ICCD 2005), pp. 519-524
  • N. Dhanwada, I. Lin and N. Vijaykrishnan, 2005, "A Power Estimation Methodology for SystemC Transaction Level Models", Proceedings of the International Conference on Hardware/Software Codesign and Synthesis (CODES + ISSS 2005), pp. 142-147
  • E. Swankowski and N. Vijaykrishnan, 2005, "Dynamic High-Performance Multi-Mode Architectures for AES Encryption", Proceedings of the Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD '05)
  • E. S. S. Reddy, V. Chandrasekhar, M. Sashikanth, K. Kamakoti Veezhinathan and N. Vijaykrishnan, 2005, "Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs", Proceedings of the Twelfth Reconfigurable Architectures Workshop (RAW 2005), pp. 172a
  • S. Srinivasan, A. Gayasen, N. Vijaykrishnan and T. Tuan, 2005, "Leakage Control in FPGA Routing Fabric", Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005), pp. 661-664
  • S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan and Y. Xie, 2005, "Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies", Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005), pp. 539-544
  • J. Hu, F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2005, "Compiler-directed Instruction Duplication for Soft Error Detection", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 1056-1057
  • G. Link and N. Vijaykrishnan, 2005, "Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip Designs", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 648-649
  • S. Srinivasan and N. Vijaykrishnan, 2005, "Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 218-223
  • S. Yang, W. Wolf, N. Vijaykrishnan and Y. Xie, 2005, "Power Attack Resistant Crypto Design: A Dynamic Voltage and Frequency Switching Approach", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 64-69
  • W.-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2005, "Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 898-899
  • Y.-F. Tsai, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2005, "Leakage-Aware Interconnect for On-Chip Network", Proceedings of the Design, Automation, and Test in Europe (DATE 2005), pp. 230-231
  • W.-L. Hung, Y. Xie, Vijaykrishnan Narayanan, C. Addo-Quaye, T. Theocharides and M. J. Irwin, 2005, "Thermal-Aware Floorplanning Using Genetic Algorithms", Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED 2005), pp. 634-639
  • J. Lee, N. Vijaykrishnan and M. J. Iriwn, 2005, "High Performance Array Processor for Video Decoding", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '05), pp. 28-33
  • H. Saputra, O. Ozturk, N. Vijaykrishnan, M. Kandemir and R. Brooks, 2005, "A Data-driven Approach for Embedded Security", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI '05), pp. 104-109
  • J.-H. Kim, D. Park, T. Theocharides, N. Vijaykrishnan and C. R. Das, 2005, "A Low Latency Router Supporting Adaptivity for On-Chip Interconnects", Proceedings of the Forty-Second Design Automation Conference (DAC '05), pp. 559-564
  • S. Mourali, T. Theocharides, L. Benini, G. DeMicheli, N. Vijaykrishnan and M. J. Irwin, 2005, "Analysis of Error Recovery Schemes for Networks-On-Chips", 22, (5), pp. 434-442
  • A. Gayasen, Vijaykrishnan Narayanan and M. J. Irwin, 2005, "Exploring Technology Alternatives for Nano-Scale FPGA Interconnects", Proceedings of the Forty-Second Design Automation Conference (DAC '05), pp. 921-926
  • E. Reddy Sundar Syam, V. Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, 2005, "Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs", Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005), pp. 1200-1203
  • E. Reddy Sundar Syam, S. M. Sashikanth, V. Chandrasehar, Vijaykrishnan Narayanan and V. Kamakoti, 2005, "Detecting SEU-caused Routing Errors in SRAM-based FPGAs", Proceedings of the Eighteenth International Conference on VLSI Design, pp. 736-741
  • T. Theocharides, G. Link, Vijaykrishnan Narayanan and M. J. Irwin, 2005, "Implementing LDPC Decoding on Network on Chip", Proceedings of the Eighteenth International Conference on VLSI Design, pp. 134-137
  • Y.-F. Tsai, Vijaykrishnan Narayanan, M. J. Irwin and Y. Xie, 2005, "Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty", Proceedings of the Eighteenth International Conference on VLSI Design, pp. 374-379
  • K. Irick, W. Xu, Vijaykrishnan Narayanan and M. J. Irwin, 2005, "A Nanosensor Array Based VLSI Gas Discriminator", Proceedings of the Eighteenth International Conference on VLSI Design, pp. 241-248
  • S. Yang, W. Wolf, W. Wang, Vijaykrishnan Narayanan and Y. Xie, 2005, "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits", Proceedings of the Eighteenth International Conference on VLSI Design, pp. 165-170
  • M. Derenzo, M. J. Irwin and N. Vijaykrishnan, 2004, "Designing Leakage-Aware Multipliers", Proceedings of the Seventeenth International Conference on VLSI Design, pp. 654-657
  • T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin and W. Wolf, 2004, "Embedded Hardware Face Detection", Proceedings of the Seventeenth International Conference on VLSI Design, pp. 133-138
  • E. Reddy Sundar Syam, S. Kanth, V. Chandrasekhar, S. Srinivasan, N. Vijaykrishnan and V. Kamakoti, 2004, "A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs", Proceedings of the 2004 IEEE International Conference on Field- Programmable Technology (FPT'04), pp. 121-128
  • J. S. Kim, C. Nicopoulos, N. Vijaykrishnan, Y. Xie and E. Lattanzi, 2004, "A Probabilistic Model for Soft-Error Rate Estimation in Combinatorial Logic", Proceedings of the First International Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems (PARTES 2004)
  • K. Unlu, V. Degalahal, M. S. Cetiner, N. Vijaykrishnan and M. J. Irwin, 2004, "Testing Neutron-Included Soft Errors in Semiconductors", Proceedings of the American Nuclear Society Winter Meeting, pp. 825-826
  • S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie and M. J. Irwin, 2004, "Improving Soft-error Tolerance of FPGA Configuration Bits", Proceedings of the International Conference on Computer Aided Design (ICCAD-2004), pp. 107-110
  • B. T. Kang, N. Vijaykrishnan and M. J. Irwin, 2004, "Analyzing Software Influences on Substrate Noise: An ADC Perspective", Proceedings of the International Conference on Computer Aided Design (ICCAD-2004), pp. 916-922
  • G. Chen, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2004, "Field-level Analysis for Heap Space Optimization in Embedded Java", Proceedings of the International Symposium on Memory Management (ISMM'04), pp. 131-142
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and R. Radhakrishnan, 2004, "Inverse Discrete Cosine Transform Architecture Exploiting Sparseness and Symmetry Properties", Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS'04), pp. 361-366
  • W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan and M. J. Irwin, 2004, "Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture", Proceedings of the International Conference on Computer Design (ICCD 2004), pp. 430-437
  • Y. Xie, L. Li, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2004, "Reliability-aware Cosynthesis for Embedded Systems", Proceedings of the Fifteenth IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP'04), pp. 41-50
  • Y.-F. Tsai, A. Hegde, N. Vijaykrishnan and M. J. Irwin, 2004, "ChipPower: An Architecture-Level Leakage Simulator", Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004), pp. 395-398
  • T. Theocharides, G. Link, N. Vijaykrishnan, M. J. Irwin and V. Srikantam, 2004, "A Generic Reconfigurable Neural Network Architecture Implemented as a Network on Chip", Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004), pp. 191-194
  • B. T. Kang, N. Vijaykrishnan, M. J. Irwin and T. Theocharides, 2004, "Power-Efficient Implementation of Turbo Decoder in SDR Systems", Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004), pp. 119-122
  • G. Chen, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, 2004, "Analyzing Object Error Behavior in Embedded JVM Environments", Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS'04), pp. 230-235
  • A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and T. Tuan, 2004, "A Dual Vdd Low-power FPGA Architecture", Proceedings of the International Conference on Field-programmable Logic and Its Applications (FPL'04), pp. 145-157
  • W. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Total Power Optimization Through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2004), pp. 144-149
  • L. Li, V. Degalahal, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Soft Error and Energy Consumption Interactions: A Data Cache Perspective", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2004), pp. 132-137
  • S. Yang, W. Wolf and N. Vijaykrishnan, 2004, "Search Speed and Power Driven Integrated Software and Hardware Optimizations for Motion Estimation Algorithms", Proceedings of the 2004 IEEE International Conference on Multimedia and Expo (ICME 2004)
  • H. Saputra, G. Chen, R. Brooks, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Code Protection for Resource-constrained Embedded Devices", Proceedings of the ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '04), pp. 240-248
  • Y.-F. Tsai, D. Duarte, N. Vijaykrishnan and M. J. Irwin, 2004, "Impact of Process Scaling on the Efficacy of Leakage Reduction Scheme", Proceedings of the International Conference on IC Design and Technology (ICICDT 2004), pp. 3-11
  • J. Lee, Vijaykrishnan Narayanan and M. J. Irwin, 2004, "Efficient VLSI Implementation of Inverse Discrete Cosine Transform", Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004), pp. 177-180
  • W. Xu, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2004, "Design of a Nanosensor Array Architecture", Proceedings of the 2004 Great Lakes Symposium on VLSI (GLSVLSI 2004), pp. 298-303
  • E. Lattanzi, A. Bogliolo, A. Gayasen, M. Kandemir, N. Vijaykrishnan and L. Benini, 2004, "Improving Java Performance by Dynamic Method Migration on FPGAs", Proceedings of the Eleventh Reconfigurable Architectures Workshop (RAW 2004), pp. p. 134
  • E. Swankoski, R. Brooks, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "A Parallel Architecture for Secure FPGA Symmetric Encryption", Proceedings of the Eleventh Reconfigurable Architectures Workshop (RAW 2004), pp. p. 132
  • V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie and M. J. Irwin, 2004, "The Effect of Threshold Voltages on the Soft Error Rate", Proceedings of the Fifth International Symposium on Quality Electronic Design (ISQED 2004), pp. 503-508
  • A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Reducing Leakage Energy in FPGAs Using Region-constrained Placement", Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays (FPGA'04), pp. 51-58
  • T. Theocharides, G. Link, E. Swankoski, N. Vijaykrishnan, M. J. Irwin and H. Schmit, 2004, "Evaluating Alternative Implementations for LDPC Decoder Check Node Function", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), pp. 77-82
  • M. Pirreti, G. Link, R. Brooks, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Fault-tolerant Algorithms for Network-on-chip Interconnect", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), pp. 46-51
  • J. S. Hu, N. Vijaykrishnan, S. Kim, M. Kandemir and M. J. Irwin, 2004, "Scheduling Reusable Instructions for Power Reduction", Proceedings of the Design Automation and Test in Europe Conference (DATE'04), 1, pp. 148-155
  • L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "A Crosstalk Aware Interconnect with Variable Cycle Transmission", Proceedings of the Design Automation and Test in Europe Conference (DATE'04), 1, pp. 102-107
  • J. S. Hu, N. Vijaykrishnan and M. J. Irwin, 2004, "Exploring Wakeup-Free Instruction Scheduling", Proceedings of the Tenth International Symposium on High Performance Computer Architecture (HPCA-10), pp. 232-243
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and W. Wolf, 2004, "An Architecture for Motion Estimation in the Transform Domain", Proceedings of the Seventeenth International Conference on VLSI Design, pp. 1077-1082
  • I. Kadayif, I. Kolcu, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2004, "Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessor", Proceedings of the Design Automation and Test in Europe Conference (DATE'04), 2, pp. 158-163
  • V. Degalahal, N. Vijaykrishnan and M. J. Irwin, 2003, "Analyzing Soft Errors in Leakage Optimized SRAM Designs", Proceedings of the Sixteenth International Conference on VLSI Design, pp. 539-545
  • J. S. Hu, N. Vijaykrishnan, M. J. Irwin and M. Kandemir, 2003, "Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch", Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI'03), pp. 127-132
  • S. Gurumurthi, J. Zhang, A. Sivasubramaniam, M. Kandemir, H. Franke, N. Vijaykrishnan and M. J. Irwin, 2003, "Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads", Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS'03), pp. 123-132
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim and W. Zhang, 2003, "Masking the Energy Behavior of DES Encryption", Proceedings of International Conference on Design Automation and Test in Europe (DATE 2003), pp. 10084-10089
  • W. Zhang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and V. De, 2003, "Compiler Support for Reducing Leakage Energy Consumption", Proceedings of International Conference on Design Automation and Test in Europe (DATE 2003), pp. 11146-11147
  • S. Gurumurthi, N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2003, "Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries", Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2003)
  • G. Chen, B. Kang, N. Vijaykrishnan, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli, 2003, "Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices", Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2003)
  • H. Schmit, T. Kroll, M. Khusid, I. Kourtev, N. Vijaykrishnan and D. Landis, 2003, "The Sandbox Experience Course", Proceedings of the International Conference on Microsystem Education, pp. 41-42
  • Y.-F. Tsai, D. Duarte, N. Vijaykrishnan and M. J. Irwin, 2003, "Implications of Technology Scaling on Leakage Reduction Techniques", Proceedings of the Fortieth Design Automation Conference, pp. 187-190
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2003, "Adapting Instruction Level Parallelism for Optimizing Leakage in VLIW Architectures", Proceedings of the Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'03), pp. 275-283
  • A. Bhatkar, R. Chandramouli, N. Vijaykrishnan and M. J. Irwin, 2003, "Computation and Transmission Energy Modeling Through Profiling for MPEG4 Video Transmission", Proceedings of the IEEE International Conference on Multimedia & Expo (ICME 2003), 1, pp. 281-284
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor and M. J. Irwin, 2003, "Estimating Influence of Data Layout Optimizations on SDRAM Energy Consumption", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 40-43
  • S. Kim, N. Vijaykrishnan, M. J. Irwin and L. K. John, 2003, "On Load Latency in Low-Power Caches", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 258-261
  • J. S. Hu, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2003, "Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 402-407
  • E. J. Kim, K. H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and C. R. Das, 2003, "Energy Optimization Techniques in Cluster Interconnects", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'03), pp. 459-464
  • H. Saputra, N. Vijaykrishnan, M. Kandemir, R. Brooks and M. J. Iriwn, 2003, "Exploiting Value Locality for Secure Energy Aware Communication", Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS'03), pp. 116-121
  • J. Lee, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli, 2003, "An Efficient Implementation of Hierarchical Image Coding", Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS'03), pp. 363-368
  • L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and I. Kadayif, 2003, "CCC: Crossbar Connected Caches for Reducing Energy", Proceedings of the Euromicro Symposium on Digital System Design (DSD'2003), pp. 41-48
  • G. Chen, G. Chen, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2003, "Energy-aware Code Cache Management for Memory-constrained Java Devices", Proceedings of the IEEE International SOC Conference (ASIC/SOC'03), pp. 179-182
  • R. Ramanarayanan, V. Degalahal, N. Vijaykrishnan, M. J. Irwin and D. Duarte, 2003, "Analysis of Soft-Error Rate for Flip-Flops and Scannable Latches", Proceedings of the IEEE International SOC Conference (ASIC/SOC'03), pp. 231-234
  • B. Kang, N. Vijaykrishnan, M. J. Irwin and D. Duarte, 2003, "Substrate Noise Detector for Noise Tolerant Mixed-Signal IC", Proceedings of the IEEE International SOC Conference (ASIC/SOC'03), pp. 279-280
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin, 2003, "Energy and Timing Characterization of VLSI Charge-pump Phase-locked Loops", Proceedings of the IEEE International SOC Conference (ASIC/SOC'03), pp. 341-344
  • A. Hegde, N. Vijaykrishnan, M. Kandemir and M. J. Iriwn, 2003, "VL-CDRAM: Variable Line Sized Cached DRAMs", Proceedings of the CODES-ISSS Merged Conference (CODES/ISSS'03), pp. 132-137
  • G. Chen, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and M. Wolczko, 2003, "Tracking Object Life Cycle for Leakage Energy Optimization", Proceedings of the CODES-ISSS Merged Conference (CODES/ISSS'03), pp. 213-218
  • V. De La Luz, A. Sivasubramaniam, M. Kandemir, M. J. Irwin and N. Vijaykrishnan, 2003, "Reducing dTLB Energy Through Dynamic Resizing", Proceedings of the Twenty-First International Conference on Computer Design (ICCD), pp. 358-363
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, B. Mathiske and M. Wolczko, 2003, "Heap Compression for Memory-constrained Java Environments", Proceedings of the Eighteenth Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'03), pp. 282-301
  • L. Li, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2003, "Adaptive Error Protection for Energy Efficiency", Proceedings of the International Conference on Computer Aided Design (ICCAD-2003), pp. 2-7
  • N. Vijaykrishnan, 2003, "Designing Energy-Efficient and Reliable Hardware", Proceedings of the IFIP International Conference on VLSI, pp. 6-9
  • S. Yang, W. Wolf and N. Vijaykrishnan, 2003, "Power Modeling of VLSI Motion Estimation Architecture", Proceedings of the Fifth Workshop on Media and Streaming Processors (MSP), held in conjunction with MICRO-6, pp. 39-49
  • V. De La Luz, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam and I. Kolcu, 2002, "Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories", Proceedings of the Seventh Asia and South Pacific Design Automation Conference (ASP-DAC '02) and the Fifteenth International Conference on VLSI Design (VLSI Design 2002), pp. 288-293
  • D. Duarte, Y.-F. Tsai, N. Vijaykrishnan and M. J. Irwin, 2002, "Evaluating Run-Time Techniques for Leakage Power Reduction", Proceedings of the Seventh Asia and South Pacific Design Automation Conference and the Fifteenth International Conference on VLSI Design (VLSI Design/ASP-DAC '02), pp. 31-38
  • G. Chen, R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko, 2002, "Tuning Garbage Collection in an Embedded Java Environment", Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8), pp. 92-103
  • S. Gurumurthi, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, T. Li and L. K. John, 2002, "Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach", Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8), pp. 141-150
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and A. Sivasubramaniam, 2002, "EAC: A Compiler Framework for High-Level Energy Estimation and Optimization", Proceedings of the International Conference on Design Automation and Test in Europe (DATE), pp. 436-442
  • J. S. Hu, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2002, "Power-Efficient Trace Caches", Proceedings of International Conference on Design Automation and Test in Europe (DATE 2002), pp. p. 1091
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin, 2002, "A Complete Phase-Locked Loop Power Consumption Model", Proceedings of International Conference on Design Automation and Test in Europe (DATE 2002), pp. p. 1108
  • I. Kadayif, N. Orr, M. Kandemir, Vijaykrishnan Narayanan and M. J. Irwin, 2002, "Instruction Selection/Scheduling Using an Energy-aware Instruction Set Architecture", Proceedings of the Sixth Workshop of Languages, Compilers, and Runtime Systems for Scalable Computers (LCR '02), pp. 1-10
  • A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2002, "Designing Energy-Efficient Software", Proceedings of the Next Generation Software Workshop, held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS 2002), pp. p. 176
  • D. Duarte, Vijaykrishnan Narayanan, M. J. Irwin and Y.-F. Tsai, 2002, "Impact of Technology Scaling on the Clock System Power", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), pp. 59-64
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2002, "Hardware-Software Co-Adaption for Data-Intensive Embedded Applications", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), pp. 20-25
  • B.-T. Kang, N. Vijaykrishnan, M. J. Irwin and R. Chandramouli, 2002, "Power Efficient Adaptive M-QAM Design Using Adaptive Pipelined Analog-to-Digital Converter", Proceedings of the International Conference on Acoustics, Speech and Signal Processing (ICASSP 2002). (CD ROM Proceedings)
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf, 2002, "Energy Savings Through Compression in Embedded Java Environments", Proceedings of the ACM/SIGDA/SIGSOFT Tenth International Conference on Hardware/Software Codesign (CODES '02), pp. 163-168
  • H. Saputra, M. Kandemir, Vijaykrishnan Narayanan, M. J. Irwin, J. S. Hu, C.-H. Hsu and U. Kremer, 2002, "Energy-Conscious Compilation Based on Voltage Scaling", Proceedings of the ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 2-10
  • J. S. Hu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra and W. Zhang, 2002, "Compiler-Directed Cache Polymorphism", Proceedings of the ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'02) and Software and Compilers for Embedded Systems (SCOPES'02), pp. 165-174
  • V. Delaluz, A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2002, "Scheduler-Based DRAM Energy Management", Proceedings of the Thirty-Ninth Design Automation Conference (DAC), pp. 697-702
  • G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko, 2002, "Adaptive Garbage Collection for Battery-Operated Environments", Proceedings of the Second USENIX JavaTM Virtual Machine Research and Technology Symposium (JVM'02), pp. 1-12
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin, H. S. Kim and G. McFarland, 2002, "Scaling of the Effectiveness of Power Reduction Schemes and the Impact of Temperature Management", Proceedings of the International Conference on Computer Design (ICCD 2002), pp. 382-387
  • L. Li, I. Kadayif, Y.-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and A. Sivasubramaniam, 2002, "Leakage Energy Management in Cache Hierarchies", Proceedings of the Eleventh International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), pp. 131-140
  • S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2002, "Predictive Precharging for Bitline Leakage Energy Reduction", Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference, pp. 36-40
  • D. Duarte, N. Vijaykrishnan and M. J. Irwin, 2002, "Impact of Technology Scaling and Packaging on Dynamic Voltage Scaling Techniques", Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference, pp. 244-248
  • R. Ramanarayanan, N. Vijaykrishnan and M. J. Irwin, 2002, "Characterizing Dynamic and Leakage Power Behavior in Flip-Flops", Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference, pp. 433-437
  • G. Esakkimuthu, N. Vijaykrishnan and M. J. Irwin, 2002, "An Analytical Power Estimation Model for Crossbar Interconnects", Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference, pp. 119-123
  • J. Zhao, R. Chandramouli, N. Vijaykrishnan, M. J. Irwin, B. Kang and S. Somasundaram, 2002, "Influence of MPEG-4 Parameters on System Energy", Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference, pp. 137-142
  • D. Charles, A. Hurson and N. Vijaykrishnan, 2002, "Improving ILP with Instruction-reuse Cache Hierarchy", Proceedings of the Fifth International Conference on Algorithms and Architectures for Parallel Processing, pp. 206-213
  • T. Li, L. K. John, A. Sivasubramaniam, N. Vijaykrishnan and J. Rubio, 2002, "Understanding and Improving Operating System Effects in Control Flow Transfer", Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), pp. 68-80
  • W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2002, "Compiler-directed Instruction Cache Leakage Optimization", Proceedings of the Thirty-Fifth Annual International Symposium on Microarchitecture (MICRO-35), pp. 208-218
  • G. Chen, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2002, "PennBench: A Benchmark Suite for Embedded Java", Proceedings of the Fifth Annual IEEE Workshop on Workload Characterization (WWC'02), pp. 71-80
  • S. Kim, Vijaykrishnan Narayanan, M. Kandemir and M. J. Irwin, 2002, "Energy-Efficient Instruction Cache Using Page-Based Placement", Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2001), pp. 229-237
  • N. Kirubanandan, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2001, "Memory Energy Characterization and Optimization for the SPEC2000 Benchmarks", Proceedings of the IEEE Fourth Annual Workshop on Workload Characterization (WWC-4) (held in conjunction with MICRO-34), pp. 193-201
  • W. Zhang, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte and Y.-F. Tsai, 2001, "Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction", Proceedings of the Thirty-Fourth Annual International Symposium on Microarchitecture (MICRO-34), pp. 102-113
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin and M. Kandemir, 2001, "Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks", Proceedings of the Fourteenth International Conference on VLSI Design, pp. 248-253
  • V. De La Luz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam and M. J. Irwin, 2001, "DRAM Energy Management Using Software and Hardware Directed Power Mode Control", Proceedings of the Seventh International Symposium on High Performance Computer Architecture (HPCA 2001), pp. 159-169
  • S. Tomar, N. Vijaykrishnan, M. Kandemir and R. Shetty, 2001, "Energy Optimization Using Object Co-Location in Java", JOSES: Java Optimization Strategies for Embedded Systems Workshop in conjunction with ETAPS 2001, pp. 9-15
  • N. Vijaykrishnan, M. Kandemir, S. Tomar, S. Kim, A. Sivasubramaniam and M. J. Irwin, 2001, "Energy Behavior of Java Applications from the Memory Perspective", Proceedings of the Java Virtual Machine Research & Technology Symposium (JVM '01), pp. 207-220
  • A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2001, "VLIW Scheduling for Energy and Performance", Proceedings of IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001), pp. 111-117
  • R. Athavale, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2001, "Influence of Array Allocation Mechanisms on Memory System Energy", Proceedings of the Fifteenth International Parallel and Distributed Processing Symposium (IPDPS 2001), pp. p. 3
  • M. Kandemir, J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif and A. Parikh, 2001, "Dynamic Management of Scratch-pad Memory Space", Proceedings of the Thirty-Eighth Design Automation Conference (DAC '01), pp. 690-695
  • I. Kadayif, T. Chinoda, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and A. Sivasubramaniam, 2001, "vEC: Virtual Energy Counters", Proceedings of ACM SIGPLAN/SIGSOFT Workshop on Program Analysis for Software Tools and Engineering (PASTE '01), pp. 28-31
  • I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin and J. Ramanujam, 2001, "Morphable Cache Architectures: Potential Benefits", Proceedings of ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), pp. 128-137
  • P. Khosla, H. Schmit, M. J. Irwin and N. Vijaykrishnan, 2001, "SoC Design Skills: Collaboration Builds a Stronger SoC Design Team", Proceedings of the 2001 International Conference on Microelectronic Systems Education (MSE 2001), pp. 42-43
  • S. Kim, Vijaykrishnan Narayanan, M. Kandemir, A. Sivasubramaniam, M. J. Iriwn and E. Geethanjali, 2001, "Power-aware Partitioned Cache Architectures", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED '01), pp. 64-67
  • N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and S. Gurumurthi, 2001, "Analyzing Energy Behavior of Spatial Access Methods for Memory-Resident Data", Proceedings of the Twenty Seventh International Conference on Very Large Databases (VLDB 2001), pp. 411-420
  • J. Hezavei, N. Vijaykrishnan, M. J. Irwin, M. Kandemir and D. Duarte, 2001, "Input Sensitive High-level Power Analysis", Proceedings of the 2001 IEEE Workshop on SiGNAL Processing Systems (SiPS 2001), pp. 149-156
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2001, "A Framework for Exploring Energy-Efficient VLIW Architectures", Proceedings of the International Conference on Computer Design (ICCD 2001), pp. 40-45
  • S. Tomar, S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2001, "Use of Local Memory for Efficient Java Execution", Proceedings of the International Conference on Computer Design (ICCD 2001), pp. 468-473
  • G. Thirugnanam, N. Vijaykrishnan and M. J. Irwin, 2001, "A Novel Low Power CAM Design", Proceedings of the Fourteenth Annual IEEE International ASIC/SOC Conference, pp. 198-202
  • D. Duarte, N. Vijaykrishnan, M. J. Irwin and M. Kandemir, 2001, "Evaluating the impact of architectural-level optimizations on clock power", Proceedings of the Fourteenth Annual IEEE International ASIC/SOC Conference, pp. 447-451
  • R. Radhakrishnan, N. Vijaykrishnan, L. K. John and A. Sivasubramaniam, 2000, "Execution Characteristics of Java Run-time Systems", Proceedings of the International Symposium on High Performance Computer Architecture (HPCA-6), pp. 387-398
  • J. Hezavei, N. Vijaykrishnan and M. J. Irwin, 2000, "A Comparative Study of Power Efficient SRAM Design", Proceedings of the Tenth Great Lakes Symposium on VLSI (GLSVLSI-2000), pp. 117-122
  • H. S. Kim, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2000, "Multiple Access Caches: Energy Implications", Proceedings of the IEEE CS Annual Workshop on VLSI (WVLSI 2000), pp. 37-42
  • A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2000, "Instruction Scheduling Based on Energy and Performance Constraints", Proceedings of the IEEE CS Annual Workshop on VLSI (WVLSI 2000), pp. 53-58
  • L. Tao, L. John, N. Vijaykrishnan, A. Sivasubramaniam, A. Murthy and J. Sabarinathan, 2000, "Using Complete System Simulation to Characterize SPECjvm98 Benchmarks", Proceedings of the International Conference on Supercomputing (ICS '00), pp. 22-33
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Ye, 2000, "Influences of Compiler Optimizations on System Power", Proceedings of Thirty-Seventh Design Automation Conference (DAC '00), pp. 304-307
  • W. Ye, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2000, "The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool", Proceedings of Thirty-Seventh Design Automation Conference (DAC'00), pp. 340-345
  • N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim and W. Ye, 2000, "Energy-Driven Integrated Hardware-Software Optimization Using SimplePower", Proceedings of the Twenty-Seventh Annual International Symposium on Computer Architecture (ISCA-2000), pp. 95-106
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and H. S. Kim, 2000, "Towards Energy Aware Iteration Space Tiling", Proceedings of ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2000), 1985, pp. 211-215
  • G. Esakkimuthu, N. Vijaykrishnan, M. Kandemir and M. J. Irwin, 2000, "Memory System Energy: Influence of Hardware-Software Optimizations", Proceedings of ISLPED'2000, pp. 244-246
  • M. Kandemir, N. Vijaykrishnan, M. J. Irwin and H. S. Kim, 2000, "Experimental Evaluation of Energy Behavior of Iteration Space Tiling", Proceedings of the Thirteenth Annual Workshop on Languages and Compilers for Parallel Computing (LCPC'00), 2017, pp. 142-157
  • R. Athavale, N. Vijaykrishnan and M. Kandemir, 2000, "Annotation Based Energy Optimization Using Array Interleaving", Proceedings of the Second Annual Workshop on Hardware Support for Objects and Microarchitectures for Java, pp. 16-20
  • D. Duarte, M. J. Irwin and N. Vijaykrishnan, 2000, "Modeling Energy of the Clock Generation and Distribution Circuitry", Proceedings of the International Conference on ASIC, pp. 261-265
  • V. Lyuboslavsky, B. Bishop, N. Vijaykrishnan and M. J. Irwin, 2000, "Design of Databus Charge-Recovery Mechanism", Proceedings of the International Conference on ASIC, pp. 283-287
  • M. J. Irwin, M. Kandemir, N. Vijaykrishnan and A. Sivasubramaniam, 2000, "A Holistic Approach to System Level Energy Optimization", Proceedings of the Tenth International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2000), 1918, pp. 88-107
  • H. S. Kim, M. J. Irwin, N. Vijaykrishnan and M. Kandemir, 2000, "Effect of Compiler Optimizations on Memory Energy", Proceedings of IEEE Workshop on Signal Processing Systems (SiPS '00), pp. 663-672
  • V. De La Luz, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2000, "Energy-Oriented Compiler Optimizations for Partitioned Memory Architectures", Proceedings of the Third International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2000), pp. 138-147
  • J. Juran, A. R. Hurson, N. Vijaykrishnan and S. Boonsiriwattanakul, 2000, "Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues", Proceedings of the Seventh International Conference on High Performance Computing (HiPC 2000), 1970, pp. 501-510
  • A. Parikh, M. Kandemir, N. Vijaykrishnan and M. J. Irwin, 2000, "Instruction Scheduling", Proceedings of the Seventh International Conference on High Performance Computing (HiPC 2000), 1970, pp. 335-344

Manuscripts

  • Y. Xiao, C. Zhang, Kevin M Irick, J. Sampson and Vijaykrishnan Narayanan, 2014, "A Task-oriented Vision System"
  • E. Swankowski, N. Vijaykrishnan, R. Brooks, M. Kandemir and M. J. Irwin, , "Symmetric Encryption in Reconfigurable and Custom Hardware", International Journal of Embedded Systems
  • E. Lattanzi, A. Bogliolo, A. Gayasen, M. Kandemir, N. Vijaykrishnan and L. Benini, , "Improving Java Performance Using Dynamic Method Migration on FPGAs", International Journal of Embedded Systems
  • E. Reddy Sundar Syam, V. Chandrasekhar, M. Sashikanth, V. Kamakoti and Vijaykrishnan Narayanan, , "Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs"

Other

  • Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan and Suman Datta, 2016, "Power rectifier using tunneling field effect transistor"
  • K. Irick, T. Theocharides, N. Vijaykrishnan and M. J. Irwin, 2006, "Real Time Embedded Face Detection", pp. 6
  • E. Reddy Sundar Syam, V. Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, 2005, "A CLB Architecture for Online Correction of SEU-based Errors in LUTs of SRAM-based FPGAs"
  • E. Reddy Sundar Syam, V. Chandrasekhar, M. Sashikanth, V. Kamakoti and N. Vijaykrishnan, 2005, "Efficient Methodology for Detection and Correction of SEU-based Interconnect Errors in FPGAs using Partial Reconfiguration"

Research Projects

  • January 2013 - December 2017, "Center for low energy systems technology (LEAST)," (Sponsor: University of Notre Dame).
  • August 2012 - July 2016, "SHF:LARGE: Collaborative Research: Architecting Next generation Memory Hierarchy: A Holistic Approach," (Sponsor: National Science Foundation).
  • September 2015 - August 2016, "A Configurable Vision Platform for Cognitive Image Analytics," (Sponsor: Intel Corporation).
  • July 2015 - June 2016, "STTR: Visible EO System and LIDAR Fusion for Low-Cost Perception by Autonomous Ground Vehicles: Phase II Option II SAF-T Program Support," (Sponsor: Toyon Research Corporation/Office of Naval Research).
  • November 2015 - December 2016, "Co-Design of Cognitive Vision Algorithms on FPGA," (Sponsor: Naval Sea Systems Command).

Honors and Awards

  • Micro's Top Picks from Computer Architecture Conferences 2015, IEEE, 2015 - 2016
  • Invited demonstration at Capitol Hill, Coalition of National Science Funding, 2016 - 2016
  • Featured Research on Big Ten Network, Big Ten Network, 2016 - 2016
  • Keynote/Invited Talks, 2016 - 2016
  • HPCA 2015 Best Paper Award, February 2015
  • 25 Years of FPL Most Influential Papers Award, International Conference on Field-programmable Logic and Applications, 2015

Service

Service to Penn State:

  • Committee Member, Search Committee, Associate Dean for Research and Innovation, 2014 - 2014
  • Member, Committee to examine the relationship between Electrical Engineering and Computer Science and Engineering, 2014 - 2014
  • Committee Member, Strategic Committee, August 2013
  • Committee Member, Publications Committee, August 2014
  • Committee Member, Personnel Committee, December 2014
  • Faculty Advisor, Vegetarian Club, 2007
  • Faculty Advisor, Unmanned Aerial Systems Group, October 2016
  • Faculty Advisor, Augmented Reality Lab, October 2016
  • Advisor, September 2015
  • Chairperson, Hiring Committee, October 2015
  • Member, Hiring Committee, Electrical Engineering, September 2015
  • , College Review Committee for Chaired and Endowed Professors, September 2015

Service to External Organizations:

  • Member, International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES 2015), Program Committee, October 2015
  • ChairSite Visit Team, NSF Expeditions in Computing Review Panel, MIT, 2014 - 2014
  • Committee Member, Executive Committee, August 2014 - August 2014
  • Committee Member, Technical Program Committee, January 2014 - January 2014
  • Committee Member, Steering Committee, July 2014 - July 2014
  • Committee Member, Technical Program Committee, March 2014 - March 2014
  • Committee Member, Technical Program Committee, November 2014 - November 2014
  • Committee Member, Program Committee, October 2014 - October 2014
  • Committee Member, Technical Program Committee, October 2014 - October 2014
  • Committee MemberTechnical Program Committee, September 2014 - September 2014
  • Member, Fellows Selection Committee, 2014
  • Chairperson, ACM Special Interest Group on Design Automation, 2015
  • Member, Executive Committee, 2015
  • Co-Chairperson, Steering Committee, 2015
  • Member, Executive Committee, 2009
  • Member, Publications Board, 2014
 


 

About

The School of Electrical Engineering and Computer Science was created in the spring of 2015 to allow greater access to courses offered by both departments for undergraduate and graduate students in exciting collaborative research in fields.

We offer B.S. degrees in electrical engineering, computer science, computer engineering and data science and graduate degrees (master's degrees and Ph.D.'s) in electrical engineering and computer science and engineering. EECS focuses on the convergence of technologies and disciplines to meet today’s industrial demands.

School of Electrical Engineering and Computer Science

The Pennsylvania State University

209 Electrical Engineering West

University Park, PA 16802

814-863-6740

Department of Computer Science and Engineering

814-865-9505

Department of Electrical Engineering

814-865-7667