Photo of Swaroop Ghosh

Swaroop Ghosh

Assistant Professor

Affiliation(s):

  • School of Electrical Engineering and Computer Science
  • Electrical Engineering
  • Computer Science and Engineering

227E Electrical Engineering west

szg212@psu.edu

814-865-1298

Research Areas:

Interest Areas:

Intersection of circuits, micro-architecture and hardware security using CMOS and post-CMOS Nano-technologies to meet the energy-efficiency and security/privacy of rapidly evolving mobile computing.

 
 

 

Education

  • BE, Indian Institute of Technology, Roorkee, India, 2000
  • MS, University of Cincinnati, 2004
  • Ph D, Purdue University, 2008

Publications

Book, Chapters

  • Anirudh Iyengar and Swaroop Ghosh, 2017, Hardware Trojans and Piracy of PCBs, Springer, pp. 125–145
  • Anirudh Iyengar and Swaroop Ghosh, 2017, Spin-Transfer-Torque RAM and Domain Wall Memory Devices, Springer, pp. 125–145
  • Swaroop Ghosh, 2011, Effect of Variations and Variation Tolerance in Logic Circuits, Springer US, pp. 83–108

Journal Articles

  • Jae-Won Jang and Swaroop Ghosh, 2017, "A Novel Interconnect Camouflaging Technique using Transistor Threshold Voltage", arXiv preprint arXiv:1705.02707
  • Seyedhamidreza Motaman, Swaroop Ghosh and Nitin Rathi, 2017, "Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM", IEEE Transactions on Emerging Topics in Computing, pp. 10
  • Rekha Govindaraj and Swaroop Ghosh, 2017, "Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell", ACM Journal on Emerging Technologies in Computing Systems (JETC), 13, (4), pp. 52
  • Seyedhamidreza Motaman, Swaroop Ghosh and Jaydeep Kulkarni, 2017, "Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing", ACM Journal on Emerging Technologies in Computing Systems (JETC), 14, (1), pp. 8
  • Asmit De, Mohammad Nasim Imtiaz Khan, Jongsun Park and Swaroop Ghosh, 2017, "Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions", Journal of Hardware and Systems Security, pp. 1–12
  • Seyedhamidreza Motaman, Swaroop Ghosh and Jaydeep P Kulkarni, 2017, "VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting", IEEE Transactions on Circuits and Systems I: Regular Papers
  • Seyedhamidreza Motaman and Swaroop Ghosh, 2016, "Adaptive write and shift current modulation for process variation tolerance in domain wall caches", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24, (3), pp. 944–953
  • Asmit De, Mohammad Nasim Imtiaz Khan and Swaroop Ghosh, 2016, "Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs", arXiv preprint arXiv:1606.00467
  • Nitin Rathi, Asmit De, Helia Naeimi and Swaroop Ghosh, 2016, "Cache bypassing and checkpointing to circumvent data security attacks on STTRAM", arXiv preprint arXiv:1603.06227
  • Jinil Chung, Kenneth Ramclam, Jongsun Park and Swaroop Ghosh, 2016, "Exploiting serial access and asymmetric read/write of domain wall memory for area and energy-efficient digital signal processor design", IEEE Transactions on Circuits and Systems I: Regular Papers, 63, (1), pp. 91–102
  • Swaroop Ghosh, Rajiv V Joshi, Dinesh Somasekhar and Xin Li, 2016, "Guest Editorial Emerging Memories?Technology, Architecture and Applications (First Issue)", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 6, (2), pp. 105–108
  • Mohammad Nasim Imtiaz Khan, Swaroop Ghosh, Radha Krishna Aluru and Rashmi Jha, 2016, "Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array", arXiv preprint arXiv:1606.00470
  • Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv Joshi and Dinesh Somasekhar, 2016, "Overview of Circuits, Systems, and Applications of Spintronics", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 6, (3), pp. 265–278
  • Anirudh Iyengar, Swaroop Ghosh and Srikant Srinivasan, 2016, "Retention Testing Methodology for STTRAM", IEEE Design & Test, 33, (5), pp. 7–15
  • Swaroop Ghosh and Kenneth Ramclam, 2016, "Robust Self-Collapsing Level-Shifter for Wide Voltage Operation", Journal of Low Power Electronics, 12, (2), pp. 117–123
  • Nitin Rathi, Helia Naeimi and Swaroop Ghosh, 2016, "Side channel attacks on STTRAM and low-overhead countermeasures", arXiv preprint arXiv:1603.06675
  • Anirudh Iyengar, Swaroop Ghosh, Kenneth Ramclam, Jae-Won Jang and Cheng-Wei Lin, 2016, "Spintronic PUFs for Security, Trust, and Authentication", ACM Journal on Emerging Technologies in Computing Systems (JETC), 13, (1), pp. 4
  • Swaroop Ghosh, 2016, "Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions", Proceedings of the IEEE, 104, (10), pp. 1864–1893
  • Walden Rhines, Anne Cirkel, Krithi Ramamritham, Xiaobo Sharon Hu, Jiang Hu, Peng Li, Chris Rowen, Shupeng Sun, Xin Li, Hongzhou Liu and others, 2015, "2015 PHIL KAUFMAN AWARD FOR DISTINGUISHED CONTRIBUTIONS TO EDA", Space, 34, (7), pp. 1096–1109
  • Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B Lal, Nick Lindert, Mesut Meterelliyoz, Randy B Osborne, Joodong Park, Shigeki Tomishima and others, 2015, "A 1 Gb 2 GHz 128 Gb/s bandwidth embedded DRAM in 22 nm tri-gate CMOS technology", IEEE Journal of Solid-State Circuits, 50, (1), pp. 150–157
  • Anirudh Srikant Iyengar, Swaroop Ghosh and Kenneth Ramclam, 2015, "Domain wall magnets for embedded memory and hardware security", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5, (1), pp. 40–50
  • Seyedhamidreza Motaman, Anirudh Srikant Iyengar and Swaroop Ghosh, 2015, "Domain wall memory-layout, circuit and synergistic systems", IEEE Transactions on Nanotechnology, 14, (2), pp. 282–291
  • Robert Karam, Ruchir Puri, Swaroop Ghosh and Swarup Bhunia, 2015, "Emerging trends in design and applications of memory-based computing and content-addressable memories", Proceedings of the IEEE, 103, (8), pp. 1311–1330
  • Swaroop Ghosh, Abhishek Basak and Swarup Bhunia, 2015, "How secure are printed circuit boards against trojan attacks?", IEEE Design & Test, 32, (2), pp. 7–16
  • Sandip Tiwari, 2015, "Memories in the Future of Information Processing", Proceedings of the IEEE, 103, (8), pp. 1247–1249
  • Anirudh Srikant Iyengar, Swaroop Ghosh and Jae-Won Jang, 2015, "MTJ-based state retentive flip-flop with enhanced-scan capability to sustain sudden power failure", IEEE Transactions on Circuits and Systems I: Regular Papers, 62, (8), pp. 2062–2068
  • Cheng-Wei Lin, Jae-Won Jang and Swaroop Ghosh, 2015, "Schmitt-Trigger-based Recycling Sensor and Robust and High-Quality PUFs for Counterfeit IC Detection", arXiv preprint arXiv:1505.03213
  • Anirudh Iyengar and Swaroop Ghosh, 2015, "Threshold voltage-defined switches for programmable gates", arXiv preprint arXiv:1512.01581
  • Jayita Das and Swaroop Ghosh, 2014, "Energy barrier model of SRAM for improved energy and error rates", IEEE Transactions on Circuits and Systems I: Regular Papers, 61, (8), pp. 2299–2308
  • Swaroop Ghosh, 2014, "Modeling of retention time for high-speed embedded dynamic random access memories", IEEE Transactions on Circuits and Systems I: Regular Papers, 61, (9), pp. 2596–2604
  • Swaroop Ghosh and Kaushik Roy, 2011, "Novel low overhead post-silicon self-correction technique for parallel prefix adders using selective redundancy and adaptive clocking", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19, (8), pp. 1504–1507
  • Swaroop Ghosh and Kaushik Roy, 2010, "Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era", Proceedings of the IEEE, 98, (10), pp. 1718–1751
  • Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, 2010, "Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.", IEEE Trans. VLSI Syst., 18, (1), pp. 53–65
  • Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis and Kaushik Roy, 2010, "Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking", IEEE transactions on very large scale integration (VLSI) systems, 18, (9), pp. 1301–1309
  • Jing Li, Aditya Bansal, Swaroop Ghosh and Kaushik Roy, 2008, "An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs", ACM Journal on Emerging Technologies in Computing Systems (JETC), 4, (3), pp. 13
  • CHANG WEN CHEN, HAMID GHARAVI and THOMAS SIKORA, 2008, "IEEE CIRCUITS AND SYSTEMS SOCIETY"
  • Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, 2007, "CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive circuit synthesis using critical path isolation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26, (11), pp. 1947–1956
  • Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, 2007, "Low-power and testable circuit synthesis using Shannon decomposition", ACM Transactions on Design Automation of Electronic Systems (TODAES), 12, (4), pp. 47
  • Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, 2006, "A novel delay fault testing methodology using low-overhead built-in delay sensor", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25, (12), pp. 2934–2943
  • Vinod Narayanan, Swaroop Ghosh, W-B Jone and Sunil R Das, 2005, "A built-in self-testing method for embedded multiport memory arrays", IEEE transactions on instrumentation and measurement, 54, (5), pp. 1721–1738
  • JH Jiang, W-B Jone, Shih-Chieh Chang and Swaroop Ghosh, 2003, "Embedded core test generation using broadcast test architecture and netlist scrambling", IEEE Transactions on Reliability, 52, (4), pp. 435–443
  • Swaroop Ghosh, Rajiv Joshi, Dinesh Somasekhar and Xin Li, , "EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS"
  • Saibal Mukhopadhyay, Abhijit Chatterjee, Sudhakar Yalamanchili and Swaroop Ghosh, , "Energy-efficient Adaptive Circuits and Systems"

Conference Proceedings

  • Mohammad Nasim Imtiaz Khan and Swaroop Ghosh, 2018, "Test Challenges and Solutions for Non-Volatile Memories", pp. 6
  • Anirudh Iyengar and Swaroop Ghosh, 2018, "Time is of the Essence: Protecting IP Secrecy, when the Functionality is Fully Reverse Engineered", pp. 4
  • Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay and Swaroop Ghosh, 2017, "Side-Channel Attack on STTRAM based Cache for Cryptographic Application", pp. 8
  • Nasim Imtiaz Khan, Swaroop Gh andsh, , 2017, "A Side-Channel Attack on STTRAM-based Cache for Cryptographic Application", pp. 4
  • Asmit De, Swaroop Gh andsh, , 2017, "CTCG: Charge-Trap Based Camouflaged Gates for Reverse Engineering Prevention", pp. 4
  • Nasim Imtiaz Khan, Swaroop Gh andsh, , 2017, "Row Hammer Attack on Non-Volatile Memory", pp. 4
  • Swaroop Ghosh and Asmit De, 2017, "Threshold Voltage Defined Multi-Input Camouflaged Gate", pp. 6
  • Rekha Govindaraj and Swaroop Ghosh, 2017, "Resistive RAM based Physically Unclonable Functions and True Random Number Generators", pp. 4
  • Hamid Motaman and Swaroop Ghosh, 2017, "Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM", pp. 4
  • Anirudh Iyengar and Swaroop Ghosh, 2017, "Side Channel Attacks on STTRAM and Low-Overhead Countermeasures", pp. 4
  • Deepak Reddy Vontela, Swaroop Gh andsh, , 2017, "Methodologies to Exploit ATPG Tools for De-camouflaging", IEEE and ACM, pp. 6
  • Alexander Holst, Jae-won Jang and Swaroop Ghosh, 2017, "Investigation of Magnetic Field Attacks on Commercial Magneto-Resistive Random Access Memory", IEEE and ACM, pp. 6
  • Radha Krishna Aluru and Swaroop Ghosh, 2017, "DROOP MITIGATING LAST LEVEL CACHE ARCHITECTURE FOR STTRAM", IEEE and ACM, pp. 4
  • Mohammad Nasim Imtiaz Khan, Anirudh S Iyengar and Swaroop Ghosh, 2017, "Novel magnetic burn-in for retention testing of STTRAM", pp. 666–669
  • Swaroop Ghosh and Xin Li, 2017, "Session 13?Security circuits and systems", pp. 1–1
  • Asmit De and Swaroop Ghosh, 2017, "Threshold voltage defined multi-input complex gates", pp. 164–164
  • Jae-won Jang, Asmit De, Swaroop Gh andsh, , 2016, "Recent Trends in Intellectual Property (IP) Protection from Reverse Engineering", IEEE and ACM, pp. 6
  • Swaroop Ghosh, Anirudh Iyen andar, , 2016, "Authentication of Printed Circuit Boards", IEEE and ACM, pp. 6
  • Anirudh Iyengar, Nitin Rathi, Swaroop Ghosh and Helia Naeimi, 2016, "Side channel attacks on STTRAM and low-overhead countermeasures", IEEE, pp. 6
  • Jae-won Jang and Swaroop Ghosh, 2016, "Improving Robustness of STTRAM Under Magnetic and Thermal Attack", pp. 4
  • Rekha Govindaraj, Swaroop Ghosh, and , , 2016, "A strong arbiter PUF using resistive RAM", pp. 4
  • Anirudh Iyengar, Swaroop Gh andsh, , 2016, "Retention Testing Methodology for STTRAM", pp. 4
  • Swaroop Ghosh, Rekha Govindaraj, and , , 2016, "A Strong Arbiter PUF using Resistive RAM", IEEE and ACM, pp. 6
  • Ithihasa Reddy Nirmala, Deepak Vontela, Swaroop Ghosh and Anirudh Iyengar, 2016, "A novel threshold voltage defined switch for circuit camouflaging", pp. 1–2
  • Rekha Govindaraj and Swaroop Ghosh, 2016, "A strong arbiter PUF using resistive RAM within 1T-1R memory architecture", pp. 141–148
  • Anirudh Srikant Iyengar and Swaroop Ghosh, 2016, "Authentication of Printed Circuit Boards"
  • Nitin Rathi, Swaroop Ghosh, Anirudh Iyengar and Helia Naeimi, 2016, "Data privacy in non-volatile cache: Challenges, attack models and solutions", pp. 348–353
  • Jinil Chung, Jongsun Park and Swaroop Ghosh, 2016, "Domain wall memory based convolutional neural networks for bit-width extendability and energy-efficiency", pp. 332–337
  • Osnat Keren, Ilia Polian and Mark M Tehranipoor, 2016, "Hardware Security (Dagstuhl Seminar 16202)", 6, (5)
  • Jae-Won Jang and Swaroop Ghosh, 2016, "Performance impact of magnetic and thermal attack on STTRAM and low-overhead mitigation techniques", pp. 136–141
  • Swaroop Ghosh, Mohammad Nasim Imtiaz Khan, Asmit De and Jae-Won Jang, 2016, "Security and privacy threats to on-chip Non-Volatile Memories and countermeasures", pp. 1–6
  • Cheng Wei Lin and Swaroop Ghosh, 2015, "A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality", pp. 32–37
  • Seyedhamidreza Motaman, Swaroop Ghosh and Jaydeep P Kulkarni, 2015, "A novel slope detection technique for robust STTRAM sensing", pp. 7–12
  • Rekha Govindaraj and Swaroop Ghosh, 2015, "Design and analysis of 6-T 2-MTJ ternary content addressable memory", pp. 309–314
  • Jae-Won Jang and Swaroop Ghosh, 2015, "Design and analysis of novel SRAM PUFs with embedded latch for robustness", pp. 298–302
  • Jinil Chung, Kenneth Ramclam, Jongsun Park and Swaroop Ghosh, 2015, "Domain wall memory based digital signal processors for area and energy-efficiency", pp. 6
  • Seyedhamidreza Motaman, Swaroop Ghosh and Nitin Rathi, 2015, "Impact of process-variations in STTRAM and adaptive boosting for robustness", pp. 1431–1436
  • Cheng Wei Lin and Swaroop Ghosh, 2015, "Novel self-calibrating recycling sensor using schmitt-trigger and voltage boosting for fine-grained detection", pp. 465–469
  • Jae-Won Jang, Jongsun Park, Swaroop Ghosh and Swarup Bhunia, 2015, "Self-correcting STTRAM under magnetic field attacks", pp. 1–6
  • Swaroop Ghosh and Rekha Govindaraj, 2015, "Spintronics for associative computation and hardware security", pp. 1–4
  • Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B Lal, Nick Lindert, Mesut Meterelliyoz, Randy B Osborne, Joodong Park, Shigeki Tomishima and others, 2014, "13.1 a 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology", pp. 230–231
  • Kenneth Ramclam and Swaroop Ghosh, 2014, "Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory", pp. 123–128
  • Anirudh Iyengar, Kenneth Ramclam and Swaroop Ghosh, 2014, "DWM-PUF: A low-overhead, memory-based security primitive", pp. 154–159
  • Anirudh Iyengar and Swaroop Ghosh, 2014, "Modeling and analysis of domain wall dynamics for robust and low-power embedded memory", pp. 1–6
  • Seyedhamidreza Motaman and Swaroop Ghosh, 2014, "Simultaneous sizing, reference voltage and clamp voltage biasing for robustness, self-calibration and testability of STTRAM arrays", pp. 1–2
  • Seyedhamidreza Motaman, Anirudh Iyengar and Swaroop Ghosh, 2014, "Synergistic circuit and system design for energy-efficient and robust domain wall caches", pp. 195–200
  • Swaroop Ghosh, 2014, "Tutorial t6b: Embedded memory design for future technologies: Challenges and solutions", pp. 14–15
  • Veena S Chakravarthi and Swaroop Ghosh, 2013, "Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies", pp. 139–149
  • Swaroop Ghosh, 2013, "Design methodologies for high density domain wall memory", pp. 30–31
  • Swaroop Ghosh, 2013, "Energy centric model of sram write operation for improved energy and error rates", pp. 1–4
  • Swaroop Ghosh, 2013, "Path to a TeraByte of on-chip memory for petabit per second bandwidth with< 5watts of power", pp. 145
  • Yih Wang, Umut Arslan, Nabhendra Bisnik, Ruth Brain, Swaroop Ghosh, Fatih Hamzaoglu, Nick Lindert, Mesut Meterelliyoz, Joodong Park, Shigeki Tomishima and others, 2013, "Retention time optimization for eDRAM in 22nm tri-gate CMOS technology", pp. 9–5
  • Yih Wang, Eric Karl, Mesut Meterelliyoz, Fatih Hamzaoglu, Yong-Gee Ng, Swaroop Ghosh, Liqiong Wei, Uddalak Bhattacharya and Kevin Zhang, 2011, "Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6 V 32nm LP SRAM", pp. 32–1
  • Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst and Kaushik Roy, 2011, "Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost", pp. 486–491
  • Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan and Kaushik Roy, 2009, "Coping with variations through system-level design", pp. 581–586
  • Swaroop Ghosh, Patrick Ndai and Kaushik Roy, 2008, "A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking", pp. 366–371
  • Swaroop Ghosh and Kaushik Roy, 2008, "Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching", pp. 635–640
  • Swaroop Ghosh, Jung-Hwan Choi, Patrick Ndai and Kaushik Roy, 2008, "O 2 C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors", pp. 189–192
  • Jing Li, Swaroop Ghosh and Kaushik Roy, 2007, "A generic and reconfigurable test paradigm using low-cost integrated poly-Si TFTs", pp. 1–10
  • Swaroop Ghosh, Pooja Batra, Keejong Kim and Kaushik Roy, 2007, "Process-tolerant low-power adaptive pipeline under scaled-Vdd", pp. 733–736
  • Swaroop Ghosh, Patrick NDai, Swarup Bhunia and Kaushik Roy, 2007, "Tolerance to small delay defects by adaptive clock stretching", pp. 244–252
  • Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, 2006, "A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation", pp. 619–624
  • Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, 2006, "Delay fault localization in test-per-scan BIST using built-in delay sensor", pp. 6–pp
  • Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim and Kaushik Roy, 2006, "Low-power and process variation tolerant memories in sub-90nm technologies", pp. 155–159
  • Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim and Kaushik Roy, 2006, "Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM", pp. 971–976
  • Arijit Raychowdhury, Swaroop Ghosh and Kaushik Roy, 2005, "A novel on-chip delay measurement hardware for efficient speed-binning", pp. 287–292
  • Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, 2005, "Shannon expansion based supply-gated logic for improved power and testability", pp. 404–409
  • Swaroop Ghosh, KW Lai, Wen-Ben Jone and Shih-Chieh Chang, 2004, "Scan chain fault identification using weight-based codes for SoC circuits", pp. 210–215

Other

  • Swaroop Ghosh, Rajiv V Joshi, Dinesh Somasekhar and Xin Li, 2016, "Emerging Memories-Technology, Architecture and Applications (First Issue)"
  • Swaroop Ghosh, 2008, "Voltage-scalable adaptive system design for low power and error resilience in nanometer technologies"

Research Projects

  • September 2017 - September 2018, "Threshold-Defined Switches for Novel Logic Engines," (Sponsor: University of South Florida (DARPA)).
  • May 2017 - May 2018, "REU:SaTC: Collaborative: Exploiting Spintronics for Security, Trust and Authentication," (Sponsor: National Science Foundation).
  • May 2017 -  , "Advancing Cybersecurity Education through Cybersecurity Training Kit," (Sponsor: Leonhard Center Applications for Individual Faculty Projects).

Honors and Awards

  • Invited to present ongoing research at CMOS emerging technology research conference, ETC CMOS, May 2017
  • Ranked 5th in Embedded Security Competition, Cybersecurity Awareness Week Conference, 2017
  • Invited to join the Editorial board member, ASP Journal of Low Power Electronics (JOLPE), 2017
  • Senior Editorial Board Member, IEEE/ACM Journal of Emerging Topics on Circuits and Systems (JETCAS), 2016
  • Invited to present ongoing research at CMOS emerging technology research conference, ETC CMOS, 2016
  • Selected to compete in finals of CSAW Embedded Security Competition, Cybersecurity Awareness Week Conference, September 2016 - November 2016
  • Invited to present research in IEEE Microprocessor Validation and Test, IEEE, October 2016 - December 2016
  • Invited to speak at ACM SIGDA dinner IEEE International Conference in Computer Aided Design, IEEE and ACM, October 2016 - November 2016
  • Ranked in Top-6 in Embedded Security Competition, Cybersecurity Awareness Week Conference, 2015
  • Invited to join as Associate Editor, IEEE Transactions on Circuits and Systems-I (TCAS-I), 2014 - 2015
  • Invited to join as Lead Guest Editor, Journal of Low Power Electronics and Applications (JLPEA), 2015
  • Outstanding Research Achievement Award, University of South Florida, August 2015
  • CoE Outstanding Research Achievement Award, University of South Florida, August 2015
  • Research on exploiting spintronics for hardware security has been spotlighted by IEEE, IEEE, 2015
  • 3rd Place in Embedded Security Competition (ESC), Cybersecurity Awareness Week Conference, 2014
  • Elevated to Senior member of IEEE, IEEE, 2013
  • Summer Research Fellowship, University of Cincinnati, 2003
  • University Merit Scholarship (1996-2000), IIT Roorkee, 1996 - 2000
  • Shamji Memorial Trust Merit Scholarship, Shamji Memorial Trust, 1998 - 2000
  • R.D. Verma Merit Scholarship, R.D. Verma Merit Scholarship Fund, 1997
  • Outstanding New Faculty Award, ACM SIGDA, June 2016
  • Spontaneous award, Intel, 2011
  • Spontaneous award, Intel, 2011
  • DARPA Young Faculty Award, DARPA, 2015
  • DARPA Young Faculty Award Director's Fellowship, DARPA, 2017
  • Departmental Recognition Award, Intel, 2012
  • Divisional Recognition Award, Intel, 2011
  • Departmental Recognition Award, Intel, 2011
  • Technology and Manufacturing Group Excellence Award, Intel, 2010
  • Best Poster Award (3rd Place), IEEE Hardware Oriented Security and Trust, 2017

Service

Service to Penn State:

  • Member, Graduate committee member, August 2016
  • Member, Safety committee member, September 2017
  • Member, Outreach committee member, September 2017
  • Co-Organizer, CSE PhD Qualifier Exam VLSI area, August 2017
  • Co-Organizer, EE PhD Qualifier Exam VLSI area, August 2017
  • Reviewer, Served as reviewer of College of Engineering Research Symposium, March 2017

Service to External Organizations:

 


 

About

The School of Electrical Engineering and Computer Science was created in the spring of 2015 to allow greater access to courses offered by both departments for undergraduate and graduate students in exciting collaborative research in fields.

We offer B.S. degrees in electrical engineering, computer science, computer engineering and data science and graduate degrees (master's degrees and Ph.D.'s) in electrical engineering and computer science and engineering. EECS focuses on the convergence of technologies and disciplines to meet today’s industrial demands.

School of Electrical Engineering and Computer Science

The Pennsylvania State University

209 Electrical Engineering West

University Park, PA 16802

814-863-6740

Department of Computer Science and Engineering

814-865-9505

Department of Electrical Engineering

814-865-7667